HDQ and 1-Wire Protocols
7-195
MPU Public Peripherals
7.15.4 Software Interface
The mapping of registers to the TI peripheral bus (TIPB) address signals is
shown in Table 7–144 and Table 7–145. The base address for the HDQ regis-
ters is FFFB:C000.
No synchronization is provided by the hardware between the register clock
domain and the state machine domain. This means that during a read the
hardware has the capability to modify the receive buffer and it is also possible
that any access to the transmit write data register corrupts the data that is
being sent if a TX is being performed.
However, these hazards can be avoided in software by observing the following
limitations:
-
A read is not performed from the interrupt status register or receive buffer
register unless the processor has been interrupted by the peripheral.
-
After the release of the go bit in the control and status register, no access
to the TX write data buffer or the control and status registers is performed
until the processor has been interrupted by the peripheral.
-
Polling of the interrupt status register is not allowed by software to
determine if an interrupt was generated.
-
No register access can be done to the module registers after the software
puts the module in power-down mode (by setting bit 5 of the control and
status register to 0), except to reenable the clock.
Table 7–144. Memory Map Summary
Address
Name
Type
8h00
TX write data
R/W
8h04
RX receive buffer
R
8h08
Control and status
R/W
8h0C
Interrupt status, read to clear
R/W
Other
Writes ignored; reads return 0
Reserved
