USB Host Controller Registers
14-24
The HC periodic start register defines the position within the USB frame where
EDs on the periodic list have priority over EDs on the bulk and control lists.
Table 14–18. HC Periodic Start Register (HcPeriodicStart)
Bit
Name
Description
Type
Reset
Value
31–14
Reserved
Reserved
13–0
PS
Periodic start
The host controller driver must program this value to be
about 10% less than the frame interval field value so that
control and bulk EDs have priority for the first 10% of the
frame; then periodic EDs have priority for the remaining 90%
of the frame.
R/W
0
The HC low-speed threshold register defines the latest time in a frame that the
USB host controller can begin a low-speed packet.
Table 14–19. HC Low-Speed Threshold Register (HcLSThreshold)
Bit
Name
Description
Type
Reset
Value
31–14
Reserved
Reserved
13–0
LST
Low-speed threshold
This field defines the number of full-speed bit times in the
frame after which the USB host controller may not start an
8-byte low-speed packet. The USB host controller only
begins a low speed transaction if the frame remaining field is
greater than the low-speed threshold.
The host controller driver must set this field to a value that
ensures that an 8-byte low-speed TD completes before the
end of the frame. When set, the host controller driver must
not change the value.
R/W
0x0628
