UART/Autobaud Control and Status Registers
12-20
Table 12–14. Receive Holding Register (RHR)
Bit
Name
Function
R/W
Reset
Value
7–0
RHR
Receive holding register
R
Undefined
The transmitter section consists of the transmit holding register (THR) and the
transmit shift register. The THR is actually a 64-byte FIFO. The host (MPU or
DSP) writes data to the THR. The data is placed into the transmit shift register
where it is shifted out serially on the TX output. If the FIFO is disabled, location
0 of the FIFO is used to store the data.
Table 12–15. Transmit Holding Register (THR)
Bit
Name
Function
R/W
Reset
Value
7–0
THR
Transmit holding register
W
Undefined
Table 12–16. FIFO Control Register (FCR)
Bit
Name
Value
Function
R/W
Reset
Value
7–6
RX_FIFO_TRIG
Sets the trigger level for the RX FIFO:
If SCR7 = 0 and TLR7:4 = 0000:
W
00
00
8 characters
01
16 characters
10
56 characters
11
60 characters
If SCR7 = 0 and TLR7:4
≠
0000,
RX_FIFO_TRIG is not considered.
If SCR7 = 1, RX_FIFO_TRIG is two LSBs of
the trigger level (1 - 63 on 6 bits) with
granularity of 1.
Notes:
1) Bits 4 and 5 can only be written when EFR[4] = 1.
2) Bits 0 to 3 can be changed only when baud clock is not running (DLL and DLH set to 0).
3) See Table 12–36 for FCR[5:4] setting restriction when SCR[6] = 1.
4) See Table 12–37 for FCR[7:6] setting restriction when SCR[7] = 1.
