Texas Instruments OMAP5910, Technical Reference Manual

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Clock Generation and Reset Control Registers
15-58
Table 15–11. MPU Idle Mode Entry 2 Register (ARM_IDLECT2) (Continued)
Bit
Reset
Value Type Description Value Name
4 EN_ LBCK Enables clock of local bus clock: P R/W 0
0 Clock stopped—it must be set to logic 1 to enable
clock activity.
1 Clock active
3 EN_ LCDCK Enables clock of LCD controller connected to MPU
TIPB: P R/W 0
0 Clock stopped—bit must be set to logic 1 to enable
clock activity
1 Clock active
2 EN_PERCK Enables peripheral clock (MPUPER_CK): P R/W 0
0 Clock stopped—bit must be set to logic 1 to
authorize clock activity
1 Clock active and can be stopped depending on
IDLTIM_ARM bit of MPU idle mode entry 1 register
(ARM_IDLECT1)
1 EN_XORPCK Enables clock of OS timer connected to MPU TIPB
and CLKIN reference peripheral clock (XORP_CK): P R/W 0
0 OS timer clock and external XORP_CK clock
stopped—bit must be set to logic 1 to authorize
clock activity
1 OS timer clock and external XORP_CK clock active
and can be stopped depending on IDLXORP_ARM
bit of MPU idle mode entry 1 register
(ARM_IDLECT1)
0 EN_WDTCK Enables clock of timer/watchdog connected to
MPU TIPB: P R/W 0
0 Clock stopped—bit must be set to logic 1 to
authorize clock activity
1 Clock supplied to timer/watchdog is active and can
be stopped depending on IDLWDT_ARM bit of
MPU idle mode entry 1 register (ARM_IDLECT1)
Note: When the timer/watchdog is configured as watchdog timer, the clock is never shutdown, regardless the value of the
IDLWDT_ARM bit or the EN_WDTCK bit.