UART/IrDA Control and Status Registers
12-82
Table 12–85. Auxiliary Control Register (ACREG) (Continued)
Bit
Reset
Value
R/W
Function
Value
Name
1
ABORT_EN
Frame abort. The host can intentionally
abort transmission of a frame by writing 1 to
this bit. Neither the end flag nor the CRC
bits are appended to the frame.
R/W
0
0
EOT_EN
EOT (end of transmission) bit. The host
writes 1 to this bit just before it writes the
last byte to the TX FIFO in set-EOT bit
frame closing method. This bit
automatically gets cleared when the host
writes to the THR (TX FIFO).
R/W
0
Table 12–86. OSC 12-MHz Select Register (OSC_12M_SEL)
Bit
Name
Function
R/W
Reset
Value
7–1
–
Reserved
R
0000000
0
OSC_12M_SEL
†
When 1, selects 6.5 division factor with a 12-MHz
system clock.
W
0
† This register is write-only and cannot be read.
Table 12–87. Module Version Register (MVR)
Bit
Name
Function
R/W
Reset
Value
7–4
MAJOR_REV
Major revision number of the module
R
†
3–0
MINOR_REV
Minor revision number of the module
R
† For example: MVR = 0x11: Version 1.1
