OMAP5910 Local Bus
14-97
Universal Serial Bus Host
Table 14–42. LB Clock Divider Register (LB_CLOCK_DIV) (Continued)
Bit
Reset
Value
Type
Description
Value
Name
2–0
LB_CLK_DIV
Local bus clock divisor:
R/W
4
010
Local bus clock is transfer controller clock
divided by 2.
100
Local bus clock is transfer controller clock
divided by 4.
110
Local bus clock is transfer controller clock
divided by 6.
Other values: Reserved
These bits control the local bus clock rate.
The clock for the local bus is derived from the
OMAP5910 traffic controller clock. The local
bus clock can be set to be transfer controller
clock divided by 2, divided by 4, or divided by
6. All other values are reserved and must not
be used.
This field must be set to a suitable value to
allow USB host controller access to system
memory. The USB host controller supports a
maximum local bus clock frequency of 50
MHz. Be sure that the divisor you select does
not result in a local bus clock frequency
greater than 50 MHz.
