Output FIFO
11-16
11.6 Output FIFO
The LCD controller contains a 2-entry by 8-bit wide output FIFO that is used
to store pixel pin data before it is driven out to the pins. Each time a modulated
pixel value is output from the dither generator, it is placed into a serial shifter.
The size of the shifter is controlled by programming the color/monochrome
select bit in the LCD control registers. The shifter can be configured to be 4 or
8 bits wide. Single-panel monochrome screens use either four or eight data
lines; single-panel color screens use eight data pins. Once the correct number
of pixels has been placed within the shifter (4-, 8-, or 2 2/3-pixel values), the
value is transferred to the top of the output FIFO. The value is then transferred
down until it reaches the last empty location within the FIFO. As values reach
the bottom of the FIFO, they are driven out one by one onto the LCD data pins
on the edge selected by the invert pixel clock (IPC) bit.
Note:
The output FIFO is bypassed in TFT mode.
