Introduction
15-6
15.1.1.3
Clock Generation and Management Module
The clock generation and management module provides the following
features:
-
Programmable clocking scheme (synchronous and synchronous scalable
modes) and power-up defaults to fully synchronous mode
-
Setup and configuration controlled by both the DSP and MPU processors
-
A single-reference clock input to one DPLL from an external source
(CLKIN). The PLL modes are configurable: lock, bypass, and idle.
-
Programmable clocks, from CLKM1, with clock and idle control capability
to the MPU and its subsystem:
J
GPIO
J
Timers
J
Other peripherals
-
Programmable clock, from CLKM2, with clock and idle control capability
to the DSP and its subsystem:
J
GPIO
J
Timers
J
Other peripherals
-
Programmable clock, from CLKM3, with clock and idle control capability
to the memory interface traffic controller (TC), including the following
modules:
J
MPU interface (MPUI)
J
System DMA controller
J
LCD controller
J
Local bus
J
MPU peripheral bridges
J
Two internal MPU TI peripheral bridges to minimize access latency
-
Programmable power saving and idle mode controls for the MPU, the
DSP, the TC, and their respective subdomains
-
Low-frequency clocks (reference clock/14) to supply watchdog timers for
the DSP and MPU
-
DMA clock request mechanism (provides DMA clock during data transfer
only)
-
Power control for external device reset/power on (flash)
-
Idle sequence controls (MPU clock domain, DSP clock domain, and TC
clock domain)
-
Programmable idle modes (MPU and DSP) for different applications
