UART/IrDA Control and Status Registers
12-64
The modem control register (MCR) [3:0] controls the interface with the
modem, data set, or peripheral device that is emulating the modem.
Table 12–53. Modem Control Register (MCR)
Bit
Name
Value
Function
R/W
Reset
Value
7
CLKSEL
0
No action
R/W
0
1
Divide clock input by 4.
6
TCR_TLR
0
No action
R/W
0
1
Enables access to the TCR and TLR
registers
5
XON_EN
0
Disable XON Any function
R/W
0
1
Enable XON Any function
4
LOOPBACK_EN
0
Normal operating mode
R/W
0
1
Enable local loopback mode (internal).
In this mode the MCR3:0 signals are looped
back into MSR7:4. The transmit output is
looped back to the receive input internally.
3
CD_STS_CH
0
In loopback mode, forces IRQ outputs to
inactive state
R/W
0
1
In loopback mode, forces IRQ outputs to
inactive state
2
RESERVED
Reserved. This bit should always be written
as 0.
R/W
0
1
RTS
0
Forces RTS output to inactive (high)
R/W
0
1
Forces RTS output to active (low)
In loopback mode controls MSR[4]
If automatic RTS is enabled, the RTS output
is controlled by hardware flow control.
0
DTR
0
Forces DTR output to inactive (high)
R/W
0
1
Forces DTR output to active (low)
Note:
Bits 5, 6, and 7 can be written only when EFR[4] = 1.
