Traffic Controller Memory Interface Registers
4-49
Memory Interface Traffic Controller
Table 4–16. EMIF Fast Interface SDRAM Configuration Register 1
(EMIFF_SDRAM_CONFIG) (Continued)
Bit
Reset
Value
Access
Description
Value
Field
1
SD_RET
SDRAM retiming:
R/W
0
0
Data is single buffered with the return clock from
SDRAM.
1
Data from SDRAM is double buffered. Data is first
clocked on return clock from SDRAM, then with
the OMAP5910 internal SDRAM clock.
0
SLRF
When set, places the SDRAM in self-refresh
mode. Mode is automatically exited upon the
generation of any SDRAM access.
R/W
0
This register is used to configure the SDRAM, interface timing, autorefresh
setup, and powerdown modes of the EMIFF interface. Table 4–17 describes
the internal organization. Table 4–18 describes the frequency range.
Table 4–17. SDRAM Internal Organization
Register Value
Memory Size
(M Bits)
Size Of Data Bus
Number Of
Banks
0000
16
8
2
0001
8
4
†
0010
16
2
0011
16
4
†
0100
64
8
2
0101
8
4
0110
16
2
0111
16
4
1000
128
8
2
†
1001
8
4
† Unavailable bank number (not supported). Do not use this setting.
Note:
Reset value = 0x2h.
