Clock Generation and Reset Control Registers
15-79
Clock Generation and System Reset Management
The status request register (STATUS_REQ_REG) indicates the status of
hardware requests. The reset value of these registers depends on what
requests are being made.
Table 15–38. Status Request Register (STATUS_REQ_REG)
Bit
Name
Value
Description
Type
Reset
Value
13
MODEM_
NSHUTDOWN
Status of RST_HOST_OUT output pin
R
12
MMC_DPLL_REQ
DPLL wake-up request from MMC
R
11
UART3_DPLL_REQ
DPLL wake-up request for UART3
R
10
UART2_DPLL_REQ
DPLL wake-up request for UART2
R
9
UART1_DPLL_REQ
DPLL wake-up request for UART1
R
8
USB_HOST_
DPLL_REQ
12-MHz clock for DPLL wake-up requested by USB
host
R
7
CAM_DPLL_
MCLK_REQ
0
No request for 48-MHz DPLL wake-up by camera
interface
R
1
Indicates request for 48-MHz DPLL wake-up by
camera interface
6
USB_DPLL_
MCLK_REQ
0
No request for 48-MHz DPLL wake-up by USB
interface
R
1
Indicates request for 48-MHz DPLL wake-up by
USB interface
5
USB_ MCLK_REQ
0
No clock request by USB host
R
1
Indicates clock request by USB host
4
SDW_ MCLK_REQ
0
No clock request by BCLKREQ
R
1
Indicates clock request by BCLKREQ
3
COM_ MCLK_REQ
0
No clock request by MCLKREQ
R
1
Indicates clock request by MCLKREQ
2
PERIPH_nREQ
Indicates status of internal peripheral clock request
signal. This is an active-low signal.
R
1
WAKEUP_nREQ
Indicates status of internal WAKEUP_nREQ signal.
This is an active-low signal.
R
0
CHIP_IDLE
Indicates status of internal CHIP_IDLE signal
R
