S&T Kontron SMARC-sXEL User Manual Download

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USER GUIDE

www.kontron.com

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SMARC-sXEL

Doc. User Guide Rev. 1.0

Doc. ID: 1068-8367

Summary of Contents for Kontron SMARC-sXEL

Page 1: ...USER GUIDE www kontron com 1 SMARC sXEL Doc User Guide Rev 1 0 Doc ID 1068 8367...

Page 2: ...SMARC sXEL User Guide Rev 1 0 www kontron com 2 This page has been intentionally left blank...

Page 3: ...be suitable for the specified use without further testing or modification Kontron expressly informs the user that this user guide only contains a general description of processes and instructions whi...

Page 4: ...y at your risk To minimize the risks associated with your products and applications you should provide adequate design and operating safeguards You are solely responsible for compliance with all legal...

Page 5: ...t Find Kontron contacts by visiting https www kontron de support and services Customer Service As a trusted technology innovator and global solutions provider Kontron extends its embedded market stren...

Page 6: ...ribed by the law may endanger your life health and or result in damage to your material ESD Sensitive Device This symbol and title informs that the electronic boards and their components are sensitive...

Page 7: ...central grounding point shall remain connected The earth ground cable shall be the last cable to be disconnected or the first cable to be connected when performing installation or removal procedures o...

Page 8: ...cessary to store or ship the product then re pack it in the same manner as it was delivered Special care is necessary when handling or unpacking the product See Special Handling and Unpacking Instruct...

Page 9: ...cription 16 SMARC Modules 16 SMARC sXEL Module 16 Variants 17 4 System Specification 18 Functional Block Diagram 18 Top Side Features 19 Rear Side Features 19 Component Main Data Specification 20 Mech...

Page 10: ...1 1 Booting the SPI Flash 66 Watch Dog 67 8 2 1 Watchdog Timer Signal 67 Power Management 67 8 3 1 Suspend States 67 8 3 2 Power Button POWER_BTN 68 8 3 3 Power Management Signals 68 9 uEFI BIOS 69 St...

Page 11: ...ification Pinout bottom side 51 Table 32 Boot Select 66 Table 33 Dual Staged Watchdog Timer Time Out Events 67 Table 34 Power Management Pins 68 Table 35 Navigation Hot Keys Available in the Legend Ba...

Page 12: ...3 Pin Power Connector 29 Figure 15 SMARC Connector 314 Pin 40 Figure 16 Main Setup Menu 70 Figure 17 Advanced Setup Menu 72 Figure 18 Chipset Setup Menu 86 Figure 19 Security Setup Menu 100 Figure 20...

Page 13: ...PC hard and software This user guide is focused on describing the special features and is not intended to be a standard PC textbook New users are recommended to observe the instruction in the user gu...

Page 14: ...the Kontron Product Label and meeting the requirements of the Limited Power Source LPS and Power Source PS2 of UL IEC 62368 1 Only products or parts that meet the requirements for Power Source PS1 of...

Page 15: ...e devices or micro circuitry Therefore proper packaging and grounding techniques are necessary precautions to prevent damage Always take the following precautions 1 Transport ESD sensitive parts in ES...

Page 16: ...C defines two different module sizes in order to offer a high level of flexibility regarding different mechanical requirements SMARC sXEL Module The SMARC sXEL is a SMARC half size module using the In...

Page 17: ...C 51017 0832 R2 4 X6425RE 8 GByte 32 GByte 2x 1 GByte LVDS HDMI DP No 40 C to 85 C The SMARC sXEL accessories are Table 2 SMARC sXEL Accessories Part Number Article Description Carrier 51300 0000 00...

Page 18: ...el Atom Industrial Elkhard Lake Intel Celeron Elkhard Lake Connector Option Standard component VCC VBAT HWM USB 0 1 3 5 USB 2 0 PWM FAN1 I2C SMB LID Sleep 14x GPIO Embedded Controller CPLD EPM1270 or...

Page 19: ...9 Top Side Features Figure 3 Top Side 1 SMARC 2 1 connector 2 Multi Chip Package MCP 3 4x LPDDR memory down 4 3 pin fan connector 5 Mounting points Rear Side Features Figure 4 Rear Side 1 SMARC 2 1 co...

Page 20: ...nterconnection Ethernet Up to 3x 1 GbE 2x GBE0 1 and 1x optional SGMII via SERDES Storage 1x SATA 6Gb s PCI Express Up to 4x PCIe x1 or Option 3x PCIe and 1x SERDES Panel Signal 1x LVDS dual channel o...

Page 21: ...les per SMARC specification There are two additional holes to enable the attachment of a thermal device such as a heatsink heatspreader The total height of the SMARC sXEL module depends on the height...

Page 22: ...SMARC sXEL User Guide Rev 1 0 www kontron com 22 Figure 7 Dimensions of SMARC sXEL Commercial Figure 8 Thickness from the Side View Commercial...

Page 23: ...atspreader plate on top of this assembly is NOT a heat sink It works as a SMARC standard thermal interface to use with a heat sink or external cooling devices External cooling must be provided to main...

Page 24: ...enerating components About 80 of the power dissipated within the module is conducted to the heatspreader plate and can be removed by the cooling solution Heatspreaders are available as an accessory fo...

Page 25: ...ade 40 C to 85 C Humidity 93 relative Humidity at 40 C non condensing according to IEC 60068 2 78 Storage Temperature Commercial grade 30 C to 85 C Industrial grade 40 C to 85 C Humidity 93 relative H...

Page 26: ...stances in electrical and electronic equipment EMC EN 55032 2015 CISPR 32 2015 Electromagnetic compatibility of multimedia equipment Emission Requirements CISPR 32 2015 German version EN 55032 2015 EN...

Page 27: ...832 R2 4PRO The MTBF estimated value assumes no fan but a passive heat sinking arrangement Estimated RTC battery life as opposed to battery failures is not accounted for and needs to be considered sep...

Page 28: ...re of the associated dangers connect the module within an access controlled ESD safe workplace Table 8 Power Supply Voltage Requirements Supply Voltage Range VDD IN 3 3 VDC to 5 25 VDC Supply Voltage...

Page 29: ...odule s mating connector is the SMARC 2 1 MXM3 3 pin Fan Connector The 3 pin fan connector powers controls and monitors a system fan Figure 14 3 Pin Power Connector The three pin connector is recommen...

Page 30: ...4 Base Frequency 1 3 GHz 1 5 GHz 2 0 GHz 1 2 GHz 1 5 GHz 1 9 GHz Turbo Frequency Max 3 0 GHz 3 0 GHz 3 0 GHz Graphic Gen 16 EU 16 EU 32 EU 16 EU 16 EU 32 EU Thermal Design Power TDP 6 W 9 W 12 W 6 W...

Page 31: ...ips are limited to 3733 MT s The module supports chip densities of 16 Gb and 32 Gb see Table 11 LPDDR4 Memory Options Table 11 LPDDR4 Memory Options Memory Configuration Speed LPDDR4 1x 16 Gbit up to...

Page 32: ...PIO4 MUX Table 14 I2S Audio SMARC Connector PCH Pin Description AUDIO_MCK AVS_I2S_MCLK1 Master Clock Output to I2S Codec s I2S0_LRCK AVS_I2S2_SFRM I2S0 Left Right Synchronization Clock I2S0_SDOUT AVS_...

Page 33: ...onfigurations PCIE_A 2 PCIe 0 0 x1 x2 x2 x4 PCIE_B 3 PCIe 0 1 x1 PCIE_C 4 PCIe 0 2 x1 x1 x2 PCIE_D 5 PCIe 0 3 x1 x1 9 SGMII PSE1 1 1 PCIeD shared with SERDES to offer 3x PCIe x1 and 1x SGMII PSE 1 for...

Page 34: ...crete common choke in series with each PHY MDI differential line pairs If this type of integrated connector module ICM is chosen 6 8 1 SGMII via SERDES option The optional LAN port SGMII for SERDES Th...

Page 35: ...odule parameter information including the module serial number and data structure and conforms to the PICMG EEEP Embedded EEPROM Specification eMMC Flash Memory option The Embedded Multimedia Flash Ca...

Page 36: ...al RTC on request such as a lithium cell or super cap on the carrier board Using the SMARC sXEL without RTC battery voltage supply may result in improper behavior Contact Kontron Support in case you p...

Page 37: ...to be 32MByte 256MBit The module s SPI voltage is 1 8V Booting takes place either from the on module SPI Flash chip or the external SPI Flash chip on the carrier board To select the SPI to boot from...

Page 38: ...efined where one port is supported by the PCH and two ports are supported by the on module CPLD The UART option is 16550 compatible and features 64 byte TX RX host controller FIFOs On chip bit rate ba...

Page 39: ...OC Input open collector Output TTL compatible IOD Input Output CMOS level Schmitt triggered Open drain output NC Not Connected O Output TTL compatible OC Output open collector or open drain TTL compat...

Page 40: ...3 3 3 3 V Input PWRGND Power Ground OD Output Open Drain NC Not Connected o 1 8 1 8 V Output DP O Differential Pair Output I O 1 8 Bi directional 1 8 V I O signal I 5 0 5 0 V Input 0 3 3 3 3 V Output...

Page 41: ...GND P19 GBE0_MDI3 Differential Pair Signals for External Transformer Carrier Series Termination Magnetics Module appropriate for 10 100 1000 GBE transceivers Carrier Parallel Termination Secondary si...

Page 42: ...Carrier Series Termination Magnetics Module appropriate for 10 100 1000 GBE transceivers Carrier Parallel Termination Secondary side center tap terminations appropriate for Gigabit Ethernet implementa...

Page 43: ...rmination Magnetics Module appropriate for 10 100 1000 GBE transceivers Carrier Parallel Termination Secondary side center tap terminations appropriate for Gigabit Ethernet implementations I O GBE MDI...

Page 44: ...e signals operate in push pull mode I O CMOS 1 8V 3 3V SDIO controller may detect SD Cards voltage level 1 8V for UHS I and 3 3V for standard and adjust its I O voltage level accordingly P40 SDIO_D1 S...

Page 45: ...QSPI Data input output I O CMOS 1 8V P58 ESPI_IO_0 SPI1_DO QSPI_IO_0 ESPI Master Data Input Output I O CMOS 1 8V In Single I O mode ESPI_IO_0 is the eSPI master output eSPI slave input MOSI whereas E...

Page 46: ...terminated on Module P78 PCIE_A_CKREQ PCIe Port A clock request IO OD CMOS 3 3V 10k PU Can be used for power saving mode on PCIe Pulled up or terminated on Module P79 GND P80 PCIE_C_REFCK Differential...

Page 47: ...f Module 100nF DC blocking capacitors shall be placed on the Carrier P100 GND P101 HDMI_CK DP1_LANE3 HDMI Port Differential Pair Data Lines O TMDS HDMI AC coupled off Module Secondary DP Port Differen...

Page 48: ...r Board P107 DP1_AUX_SEL Strapping Signal to Enable Either HDMI or DP Output I CMOS 1 8V PD 1M Pulled to GND on Carrier for DP operation in Dual Mode DP implementations Driven to 1 8V on Carrier for H...

Page 49: ...On x86 systems these serve as SMB CLK P122 I2C_PM_DAT Power management I2C bus DATA I O OD CMOS 1 8V PU 2k2 On x86 systems these serve as SMB DATA P123 BOOT_SEL0 Input straps determine the Module boo...

Page 50: ...P142 GND P143 CAN0_TX CAN Port 0 Transmit Output O CMOS 1 8V P144 CAN0_RX CAN Port 0 Receive Input I CMOS 1 8V P145 CAN1_TX CAN Port 1 Transmit Output O CMOS 1 8V P146 CAN1_RX CAN Port1 Receive Input...

Page 51: ...AT which requires PU MIPI CSI 3 0 uses CSI0_TX no PU required S8 CSI0_CK CSI0 differential clock input point to point I D PHY S9 CSI0_CK CSI0 differential clock input point to point I D PHY S10 GND S1...

Page 52: ...MDI0 B1_D A TX TX MDI1 B1_D B RX RX MDI2 B1_D C MDI3 B1_D D S21 GBE1_MDI1 Differential Pair Signals for External Transformer Carrier Series Termination Magnetics Module appropriate for 10 100 1000 GB...

Page 53: ...ier Series Termination Magnetics Module appropriate for 10 100 1000 GBE transceivers Carrier Parallel Termination Secondary side center tap terminations appropriate for Gigabit Ethernet implementation...

Page 54: ...PCIe link D receive data pair I PCIE Series AC coupled off Module 75 265nF depending on PCIe generation Differential SERDES 0 Receive Data Pair I PCIE Series AC coupled on Carrier S34 GND S35 USB4 US...

Page 55: ...nition Audio data out to codec O CMOS 1 8V 1 5V SMARC requires 1 5V or 1 8V HD Audio signaling Please check with your Module vendor if 1 5V or 1 8V are supported and use an audio codec that is capable...

Page 56: ...whereas ESPI_IO_1 is the SPI master input eSPI slave output MISO QSPI Data input output I O CMOS 1 8V S58 ESPI_RESET ESPI Reset O CMOS 1 8V Reset the eSPI interface for both master and slaves eSPI Re...

Page 57: ...PCIE Series AC coupled on Module 75 265nF depending on PCIe generation Differential SERDES 1 Transmit Data Pair O PCIE Series AC coupled on Module S82 PCIE_C_TX SERDES_1_TX Differential PCIe link C t...

Page 58: ...y DP Port Differential Pair Data Lines O DP AC coupled off Module 100nF DC blocking capacitors shall be placed on the Carrier S104 USB3_OTG_ID Input Pin to Announce OTG Device Insertion on USB 3 2 Por...

Page 59: ...pairs at the endpoint of the signal path usually on the display assembly Secondary 4 Lane eDP Differential Pair Data Lines O DP AC coupled off Module 100nF DC blocking capacitors shall be placed on t...

Page 60: ...DSI1_D2 Secondary LVDS Channel Differential Pair Data Lines O LVDS 100 ohm differential termination across the differential pairs at the endpoint of the signal path usually on the display assembly Se...

Page 61: ...r Data Lines O LVDS 100 ohm differential termination across the differential pairs at the endpoint of the signal path usually on the display assembly Primary 4 Lane eDP Differential Pair Data Lines O...

Page 62: ...nce S133 LCD0_VDD_EN Primary LVDS Channel Power Enable O CMOS 1 8V Active high Primary Panel Power Enable O CMOS 1 8V Active high Primary Panel Power Enable O CMOS 1 8V Active high S134 LVDS0_CK eDP0_...

Page 63: ...8V PU 2k2 Possible EDID EEPROM Address conflicts may occur if multiple displays are implemented Optional eDP panel information is usually exchanged via the eDP auxiliary pair DDC Data Line Used for F...

Page 64: ...Driven by OD on Carrier S153 CARRIER_STBY The Module shall drive this signal low when the system is in a standbypower state O CMOS 1 8V On x86 designs this pin should utilize the SUS_S3 signal S154 C...

Page 65: ...S157 TEST Held Low by Carrier to Invoke Module Vendor Specific Test Functions I OD CMOS 1 8 to 5V PU vendor specific value Module must implement PU but actual value is depended on particular Module de...

Page 66: ...t Float Carrier SPI CS0 4 Float GND GND Module NAND NOR 5 Float GND Float Remote boot GBE serial 6 Float Float GND Module eMMC flash 7 Float Float Float Module SPI Booting takes place either from the...

Page 67: ...for further help Table 33 Dual Staged Watchdog Timer Time Out Events 0000b No action Stage is off and will be skipped 0001b Reset Restarts the module and starts a new POST and operating system 0101b D...

Page 68: ...on input from Carrier Board Carrier to float the line in in active state Active low level sensitive Should be debounced on the Module LID S148 Lid open close indication to Module Low indicates lid clo...

Page 69: ...r on the board 2 Wait until the first characters appear on the screen POST messages or splash screen 3 Press the DEL key 4 If the uEFI BIOS is password protected a request for password will appear Ent...

Page 70: ...ilable functions Configurable functions are displayed in blue Functions displayed in black provide information about the status or the operational configuration The right frame displays a Help window...

Page 71: ...or information PCH information Package information and ME Firmware information System Language Choose the system default language English Platform Information Read only field Module Information Produc...

Page 72: ...function Default settings are in bold Table 37 Advanced Setup Menu Sub screens and Functions Sub screen Next Level Sub screens Description RC ACPI Settings Native PCIE Enable Bit PCIE Native Control...

Page 73: ...dware Prefetcher Turns ON OFF the MLC streamer prefetcher Enabled Disabled Adjacent Cache Line Prefetch Turns ON OFF prefetching of adjacent cache lines Enabled Disabled Intel VMX Virtualization Techn...

Page 74: ...3 reads 0 indicating no support for energy efficient policy setting When set to 1 enables access to ENERGY_PERFORANCE_BIAS MSR 1B0h and CPUID function 6 ECX 3 will read 1 indicating Energy Efficient...

Page 75: ...abled Disabled Platform PL1 Enable Platform power limit 1 programming Enable activates the PL1 value to be used by the processor to limit the average power of given time window Enabled Disabled Platfo...

Page 76: ...When disables ME will not unconfigured on RTC clear Enabled Disabled Extended CSME Measured to TPM PCR Read only field Enabled Disabled Core BIOS Done Message Enables or disable the core BIOS Done mes...

Page 77: ...mal control circuit must be activated 0 TCC Offset Time Window For Running Average Temperature Limits RATL feature the offset time range is 5 ms to 448 s Disabled 5ms 10ms 384sec 488sec TCC Offset Cla...

Page 78: ...led Sub screen Next Level Sub screens Description ACPI D3Cold Settings ACPI D3Cold Support Enabled Disabled VR Ramp up Delay Delay between subsequent VR ramp ups if they are all turned on at the same...

Page 79: ...ionality Enabled Disabled SATA Port 4 Control the SATA port RTD3 functionality Enabled Disabled SATA Port 5 Control the SATA port RTD3 functionality Enabled Disabled PCIe Remapped CR1 PCIe RTD3 setup...

Page 80: ...ports both with the default set to TPM 2 0 devices if not found TPM 1 2 devices will be enumerated TPM 1 2 TPM 2 0 Auto Sub screen Next Level Sub screens Description ACPI Settings Enable ACPI Auto Con...

Page 81: ...ers to identify the power status of the system Enabled Disabled SMbus Device ACPI Mode SM bus device is hidden or visible in OS Hidden Normal CPLD Device ACPI Mode CPLD device is hidden or visible in...

Page 82: ...re External Fan Fan Control Sets fan control mode where disable totally stops the fan Disabled Manual Auto Fan Pulse Number of pulses the fan produces during one revolution range 1 4 2 Fan Trip Point...

Page 83: ...3F8h IRQ 4 Possible Allows the user to change the device s resource settings New settings are reflected on the setup page after system restart Use Automatic Settings IO 3F8h IRQ 4 IO 3F8h IRQ 3 4 5 7...

Page 84: ...Transfer Time outs Time out value for control Bulk and interrupt transfers 1 sec 5 sec 10 sec 20 sec Device Reset Time out USB Mass Storage device start unit command time out 10 sec 20 sec 30 Sec 40 s...

Page 85: ...fter the change action you may need to enter the password when you enter UI Input an empty password can clean old admin password then no need to input password to enter UI Sub screen Next Level Sub sc...

Page 86: ...re Configuration option Note Ignore policy update STR_FW_CONFIG_DEFAULT_VALUE is to skip policy update and will only work on a platform Ignore Policy Update Production Test Sub screen Next Level Sub s...

Page 87: ...nfig MCR ULT safe Configuration for P0 Enabled Disabled Safe Mode Support Used for changes WAs that may affect a stable MRC Enabled Disabled Maximum Memory Frequency Maximum frequency MHz must divide...

Page 88: ...s Enabled Disabled Memory Remap Memory remap above 4 GB Enabled Disabled Fast Boot Fast path through the MRC Enabled Disabled Train On Warm Boot Training on warm boot Enabled Disabled BDAT Memory Test...

Page 89: ...e Enabled Disabled IOP VTD Enable Enabled Disabled CPU Crash Log Device 10 Enabled Disabled CRID Support SA CRID and TCSS CRID control for Intel SIPP Enabled Disabled Above 4 GB MMIO BIOS Assignment E...

Page 90: ...Disable L0s L1 LOsL1 Auto L1 Sub states PCI express L1 sub state settings Disabled l1 1 l1 1 L1 2 ACS Access Control Service extended capabilities Enabled Disabled PTM Precision Time Measurement Enabl...

Page 91: ...I O Reserved IO Range 4K 8K 12K 16K 20K for this root bridge 4 PCH PCIe LTR Configuration LTR PCIe latency reporting Enabled Disabled Snoop Latency Override Snoop latency override for PCH PCIe Disabl...

Page 92: ...Disabled Sub screen Next Level Sub screens Description PCH IO Configuration SATA Configuration SATA Controllers Enable disable SATA device Enabled Disabled SATA Mode Selection Determines how the SATA...

Page 93: ...design before enabling Enabled Disabled SATA Port 0 RXPolarity Enable disable SATA Port 0 RXPolarity Disable is default check module design before enabling Enabled Disabled DITO Configuration Enabled...

Page 94: ...M protection of Flash Enabled Disabled Sub screen Next Level Sub screens Description PCH IO Configuration HD Audio Configuration HD Audio Controls detection of the HD audio device Enables or disable H...

Page 95: ...0 UART 0 00 30 00 cannot be enabled when I2S Audio codec is enabled Disabled Enabled Communication port COM Serial IO UART1 Settings Hardware Flow Control Enable configures two additional GPIO pads fo...

Page 96: ...host owned because SPI0 is the function 0 of the device SPI0 has pin conflict with PWM TGPIO10 14 39 serial IO SPI2 SPI1 has pin conflict with PWM TGPIO32 35 SPI2 has pin conflict with serial IO SPI0...

Page 97: ...ne 8 PSE TSN GBE 0 Multi VC Enable or disable TSN Multi Virtual Channels TSN GBE must be host owned Enabled Disabled PSE TSN GBE 0 SGMII Support Enable or disable Modphy support for SGMII mode with th...

Page 98: ...isables PCH ACPI timer stops TCO timer and ACPI WDAT table will not be published Enabled Disabled PCIe PLL SSC PCIe PLL SSC percentage Auto Keep HW default no BIOS override range 0 0 to 2 0 Auto 0 0 0...

Page 99: ...2x24 Custom PAID Panel Channel Mode For internal LVDS EDID 1 3 detection select the panel channel Mode Auto chooses the setting will be determined during the next start and the switch will be set to...

Page 100: ...ens Description Setup Administrator Password Sets administrator password User Password Sets user password Secure Boot Secure Boot Enable to activate Platform key PK is enrolled and the system is in us...

Page 101: ...re_List b EFI_cert_X509 DER c EFI_CERT_RSA2048 bin d EFI_CERT_SHAXXX 2 Authenticated UEFI variable 3 EFI PE COFF Image SHA256 Key Source Factory External Mixed Key Exchange Keys Authentication Signatu...

Page 102: ...imeout Number of seconds that the firmware waits for setup activation key The value 65535 0xFFFF means an indefinite wait 1 Bootup NumLock State Selects keyboard NumLock state ON OFF Quiet Boot Enable...

Page 103: ...umper to save new changes on BIOS setting The following table shows the Save and Exit sub screens and describes the function Table 41 Save and Exit Setup Menu Sub screens and Functions Sub screen Desc...

Page 104: ...ww kontron com 104 Sub screen Description Save as User Defaults Saves changes done so far as user defaults Yes No Restore User Defaults Restores user defaults to all setup options Yes No Boot Override...

Page 105: ...the equipment is repaired or replaced within the stipulated warranty period Follow these steps before returning any product to Kontron 1 Visit the RMA Information website http www kontron com support...

Page 106: ...dent liability obligations in the event of damage caused to the product due to failure to observe the following Safety instructions within this user guide Warning labels on the product and warning sym...

Page 107: ...onitor I2C Inter Integrated Circuit IOL IPMI Over LAN IOT Internet of Things IPMI Intelligent Platform Management Interface LPS Limited Power Source LVDS Low Voltage Differential Signaling MAC Media A...

Page 108: ...ucts and tailor made solutions based on highly reliable state of the art embedded technologies Kontron provides secure and innovative applications for a variety of industries As a result customers ben...

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