UART/Autobaud Control and Status Registers
12-23
UART Devices
Table 12–18. Line Control Register (LCR)
Bit
Name
Value
Function
R/W
Reset
Value
7
DIV_EN
0
Normal operating condition
R/W
0
1
Divisor latch enable. Allows access to
DLL, DLH, and other registers (see the
register mapping).
6
BREAK_EN
Break control bit.
R/W
0
0
Normal operating condition
1
Forces the transmitter output to go low
to alert the communication terminal
5
PARITY_TYPE2
Selects the forced parity format (if LCR3
= 1)
If LCR5 = 1 and LCR4 = 0, the parity bit
is forced to 1 in the transmitted and
received data.
If LCR5 = 1 and LCR4 = 1, the parity bit
is forced to 0 in the transmitted and
received data.
R/W
0
4
PARITY_TYPE1
0
Odd parity is generated (if bit 3 = 1).
R/W
0
1
Even parity is generated (if bit 3 = 1).
3
PARITY_EN
0
No parity
R/W
0
1
A parity bit is generated during
transmission and the receiver checks for
received parity.
2
NB_STOP
Specifies the number of stop bits:
R/W
0
0
1 stop bits (word length = 5, 6, 7, 8)
1
1.5 stop bits (word length = 5)
1
2 stop bits (word length = 6, 7, 8)
Note:
As soon as LCR[6] is set to 1, the RX line is forced to 0 and remains in this state as long as LCR[6] = 1.
