OMAP5910 Local Bus MMU
14-101
Universal Serial Bus Host
14.7.12
Local Bus Virtual Addressing
When an MPU, DSP, or DMA access to the local bus causes a local bus abort
interrupt, the interrupt service routine for MPU level 1 interrupt IRQ29 must
read the LB IRQ input register (LB_IRQ_INPUT) to clear the IRQ and then
must clear the IRQ at the MPU level 1 interrupt handler input IRQ29.
14.8 OMAP5910 Local Bus MMU
The local bus memory management unit (MMU) is used by the local bus inter-
face for address management of bus cycles initiated by the OMAP5910 USB
host controller. The local bus MMU manages local bus virtual addresses, in-
cluding conversion of local bus virtual addresses to physical addresses and
monitoring of access permissions. The local bus MMU can be initialized by the
MPU to allow the USB host controller to access the full range of OMAP5910
system memory. A detailed functional description of the MMU architecture can
be found in Chapter 2, MPU Subsystem.
The local bus MMU includes the following basic blocks:
-
A 32-entry translation look aside buffer (TLB)
-
Walking table logic
-
Registers for recording fault status and fault address
When properly configured and enabled, the walking table logic automatically
performs the address conversion from local bus virtual address to physical
address (for USB host controller accesses to system memory). Alternately, the
walking table logic can be disabled, which allows the MPU to perform local bus
virtual address translation under software control.
The local bus MMU is configured via registers which are on the MPU private
peripheral bus. The MPU is responsible for correctly configuring the local bus
MMU memory mapping functions.
The local bus MMU operates much like the MPU and DSP MMUs. The local
bus MMU does not use the upper 4 bits of the local bus virtual address (they
are ignored by the local bus MMU hardware) and does not support the prefetch
feature.
OMAP5910 Local Bus / OMAP5910 Local Bus MMU
