Texas Instruments OMAP5910, Technical Reference Manual

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Clock Generation and Reset Control Registers
15-76
The interrupt status register (IT_STATUS_REG) provides the status and
source of ULPD interrupts.
Table 15–33. Interrupt Status Register (IT_STATUS_REG)
Bit Name Description Type
Reset
Value
3 IT_WAKEUP_USB Wake-up interrupt from USB function is shared with
ULPD gauging interrupt (MPU level 2 interrupt IRQ_24). R 0x0
2 OVERFLOW_32 Overflow occurred on 32-kHz counter during gauging. R 0x0
1 OVER-
FLOW_HI_FREQ Overflow occurred in high-frequency counter during
gauging versus high frequency clock. R 0x0
0 IT_GAUGING End of gauging interrupt. Informs the MPU that gauging
is stopped and that it can read value of high and low
frequency counters. R 0x0
The clock control register (CLOCK_CTRL_REG) manages clock output and
inactive values.
Table 15–34. Clock Control Register (CLOCK_CTRL_REG)
Bit Name Value Description Type
Reset
Value
5 DIS_USB_PVCI_
CLK 0 Enables USB function clock for FAC counter R/W 0x0
1 Disables USB function clock for FAC counter
4 USB_MCLK_EN 0 Disables USB.CLKO R/W 0
1 Enables USB.CLO
3 RESERVED Reserved. This bit should always be written as 0. R/W 0x0
2 SDW_MCLK_INV 0 BCLK is low when inactive. R/W 0
1 BCLK is high when inactive.
1 COM_MCLK_ INV 0 MCLK is low when inactive. R/W 0
1 MCLK is high when inactive
0 MODEM_32K_ EN 0 Disables 32-kHz on UART clock R/W 0
1 Enables 32-kHz on UART clock