Clock Generation and Reset Control Registers
15-67
Clock Generation and System Reset Management
The DSP idle mode entry 2 register (DSP_IDLECT2) disables the clock
domains individually and independently of the DSP state.
Table 15–21. DSP Idle Mode Entry 2 Register (DSP_IDLECT2) – Offset Address: 0x08
Bit
Name
Value
Description
Type
Reset
Value
15–6
RESERVED
Reading these bits gives undefined values. Writing
to them has no effect.
5
EN_TIMCK
Enables DSP timer clock (DSPTIM_CK)
R/W
0
0
DSPTIM_CK clock is stopped. This bit must be set
to logic 1 to enable clock activity.
1
DSPTIM_CK clock is active and can be stopped,
depending on DSP_IDLECT1 IDLTIM_DSP bit.
4
EN_GPIOCK
Enables GPIO peripheral clock (GPIO_CK).
R/W
0
0
GPIO_CK clock is stopped. The bit must be set to
logic 1 to enable clock activity.
1
GPIO_CK clock is active. The GPIO_CK clock must
be disabled by setting EN_GPIOCK = 0 before
sleep modes can be entered.
3–2
RESERVED
Reserved. These bits should always be written as 0.
1
EN_XORPCK
Enables DSPXOR_CK reference clock.
R/W
0
0
The DSPXOR_CK clock is stopped. The bit must be
set to logic 1 to enable clock activity.
1
The DSPXOR_CK clock is active and can be
stopped, depending on DSP_IDLECT1
IDLXORP_DSP bit.
0
EN_WDTCK
Enables DSPWDT_CK reference clock.
R/W
0
0
The DSPWDT_CK clock is stopped. The bit must be
set to logic 1 to enable clock activity.
1
The DSPWDT_CK clock is active and can be
stopped, depending on DSP_IDLECT1
IDLWDT_DSP bit.
