Clock Generation and Reset Control Registers
15-64
DSP Base word address: 0x4000 – Bit Width: 16
Table 15–17. DSP Clock/Reset/Power Mode Control Registers
Register Name
Descriptions
R/W
Size
DSP
Address
MPU
Address
Reset
Value
DSP_IDLECT1
DSP idle select 1
R/W
16 bits
00:4002
E100:8004
0x0000
DSP _IDLECT2
DSP idle select 2
R/W
16 bits
00:4004
E100:8008
0x0000
Reserved
00:4006
0x0000
Reserved
00:4008
0x0000
DSP _RSTCT2
DSP reset control
R/W
16 bits
00:400A
E100:8014
0x0000
DSP _SYSST
DSP system status
R/W
16 bits
00:400C
E100:8018
0x0000
Reserved
00:400E
0x0000
Reserved
00:4010
0x0000
The DSP domain peripheral clock setup and the external module reset
functions are controlled by the DSP through these registers.
The DSP clock control register (DSP_CKCTL) defines the frequency selection
for the DSP_GPIO_CK and the DSPTIM_CK.
Table 15–18. DSP Clock Control Register (DSP_CKCTL) – Offset Address: 0x00
Bit
Name
Value
Description
Type
Reset
Value
15–9
RESERVED
Reading these bits gives an undefined value.
Writing to them has no effect.
8
TIMXO
Selects either a CK_GEN2 frequency clock or input
reference clock (CLKIN) to supply DSP timer
peripherals.
R/W
1
0
The DSPTIM_CK clock frequency is the input
reference clock.
1
DSPTIM_CK frequency is issued from CK_GEN2/2.
