Clock Generation and Reset Control Registers
15-71
Clock Generation and System Reset Management
The mode (bypass or lock) and the frequency selections are defined via
memory mapped control register bits. Programming is performed through the
TIPB and is initiated the MPU.
The idle mode is entered upon an asynchronous idle signal request (idle).
Note:
The DPLL idle mode entry/exit timing is dependent upon the input/output
frequency ratio selection.
The input reference clock signal must be active for (at least) 24 input clock
cycles from the idle request (idle rising edge) before the DPLL idle setup has
completed (idle_ack high).
Once in idle mode, the clock source can be stopped (either in a high or a low
level), but the reference clock source must be restarted before releasing the
idle mode.
When the idle mode is exited, the DPLL is set in bypass mode and the output
clock signal is valid after a maximum of 10 input reference clock cycles. If the
DPLL was synthesizing a frequency prior to enter the idle state, then the
DPLL switches from the bypass mode (frequency set /BYPASS_DIV) to the
synthesizer mode (frequency set/PLL_MULT and PLL_DIV) when the lock
state is reacquired.
Table 15–24 lists the DPLL control registers. Table 15–25 describes the
register bits.
The MPU base addresses for the DPLL control registers are:
DPLL1:
0xFFFE:CF00
Bit width:
16 bits
Writing to the control register (CTL_REG) causes the DPLL to immediately
switch to the bypass mode if not in idle state. If the PLL_ENABLE bit of the
control register is set, it begins its sequence to enter the locked mode. This
prevents being able to change the multiple or divide values without reentering
the DPLL lock sequence.
Table 15–24. DPLL Control Registers
Register Name
Descriptions
R/W
Size
Offset
Reset Value
CTL_REG
DPLL control register
R/W
16 bits
x00
0x2002
