McBSP3
9-19
DSP Public Peripherals
9.4.4.4
Transmit Control Register Configuration
The values of RWDLEN1, 2 and XWDLEN1, 2 must be set to the same value
in SPI mode.
DSP_Write(0x0000) => XCR1; set up XCR1 per below configuration.
Table 9–19. Transmit Control Register 1 Configuration (DSP_Write(0x0000) => XCR1)
Bit
Config Value
Description
15
0b
Reserved
14–8
000 0000b
Set transmit frame length as one word per frame
7–5
000b
Set transmit word length as 8 bits per frame
4–0
0 0000b
Reserved
DSP_Write(0x0000) => XCR2; set up XCR2 per below configuration.
Table 9–20. Transmit Control Register 2 Configuration (DSP_Write(0x0000) => XCR2)
Bit
Config Value
Description
15
0b
Set single-phase frame
14–8
000 0000b
Don’t care for single phase frame
7–5
000b
Don’t care for single phase frame
4–3
00b
Set no companding data and transfer start with MSB first
2
0b
Set FSX not ignore after the first resets the transfer
1–0
00b
Set data delay as 0 bit