Multichannel Serial Interfaces
9-45
DSP Public Peripherals
The clock frequency register is used only in master mode when the interface
generates the serial clock (see Table 9–30).
Table 9–30. Clock Frequency Register (CLOCK_FREQUENCY_REG)
Bit
Name
Description
Access
Hardware
Reset
15–11
Unused
R
0000 0
10–0
clk_freq
Division factor of 12-MHz reference clock
(2
<=
clk_freq
<=
2047)
In master mode, this register defines the transmission
baud rate from a frequency ratio based on a 12-MHz
reference clock. The transmission clock frequency can
be programmed from 5.8 kHz to 6 MHz in steps or
increments of 83 ns.
Clock frequency = 12 MHz / clk_freq with 2
<=
clk_freq
<=
2047.
R/W
000 0000 0000
CLK_FREQ: division factor of 12-MHz reference clock (2
<=
clk_freq
<=
2047)
In master mode, this register defines the transmission baud rate from a
frequency ratio based on a 12-MHz reference clock. The transmission clock
frequency can be programmed from 5.8 kHz to 6 MHz in steps or increments
of 83 ns.
Clock frequency = 12 MHz / clk_freq with 2
<=
clk_freq
<=
2047.
Table 9–31. Oversized Frame Dimension Register (OVER_CLOCK_REG)
Bit
Name
Description
Access
Hardware
Reset
15–10
Unused
R
0000 00
9–0
over_clock
Overhead clock periods in frame duration
(0
=
OVER_CLOCK
=
1023)
R/W
00 0000 0000
