Power Management
15-27
Clock Generation and System Reset Management
The following rules ensure that sufficient time is allowed:
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Clock reset module needs at least four reference clock cycles (12-MHz
clock) and two MPU clock cycles to send a sleep request to the MPU.
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The MPU needs at least three MPU clock cycles to send back an acknowl-
edge after receiving the sleep request. This is true even if there are no
access requests coming from MPU before or after the sleep request. The
sleep request is generated from the register write to IDLECT1 Bit 11.
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Add NOP instructions to make sure there is no request coming from the
MPU by considering the worst case scenario. This scenario is: MMU and
I–cache enabled, a MMU TLB miss (requiring a L1 and L2 fetch), and an
I–cache miss, as follows:
J
Four read strobes for the instruction fetch (a line load of 4 words)
J
One read strobe for TLB Miss L1 descriptor fetch
J
One read strobe for TLB Miss L2 descriptor fetch
This requires six read strobes, which need N number of MPU clock cycles.
N depends on the type of memory from which the reads are being made.
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There is a software solution to avoid these extra N MPU clock cycles due
to the read strobes. This solution requires only I-Cache be enabled. By
changing the loop count value (CMP R2) we can increase/decrease
number of cycles, as shown in Figure 15–12.
