Power Management
15-47
Clock Generation and System Reset Management
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The MPU_RST input pin has a hysteresis type input buffer.
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De-bouncing is not implemented
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The pin has a minimum pulse width requirement (refer to appropriate data-
sheet all timing requirements).
When a warm reset condition occurs, the RST_OUT output pin is asserted
active low. The RST_OUT output pin is always enabled (the RST_OUT
function cannot be disabled). Refer to the appropriate device datasheet for
complete timing characteristics of RST_OUT relative to MPU_RST.
The assertion of MPU_RST (warm reset) has the following effects:
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Always forces a re-boot of the MPU processor
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Shared GPIO logic and registers are reset.
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ULPD registers are reset except for the following cases:
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IT_STATUS_REG: pending interrupts could possibly survive the
warm-reset and become posted again after the reset condition.
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DPLL register is not reset.
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SETUP_ANALOG_CELL3_ULPD1_REG is not reset.
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ARMIO_CTL and DATA_OUT registers associated with MPUIO logic are
NOT reset and retain their previous values.
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The appropriate bits within the ARM_SYSST register are set to indicate
that the reset event was due to a warm-boot (the MPU can read
ARM_SYSST to differentiate a warm-boot from a power on reset).
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Self-refresh of external SDRAM is initiated if this function is enabled via
the appropriate Traffic Controller registers.
The following registers /logic are unaffected by a warm reset condition and
retain their previous state:
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OMAP5910 Configuration Registers associated with device pin
multiplexing
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OMAP5910 Configuration Registers which enable/disable pullup/
pulldown resistors on the device pins.
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MPU Level 2 interrupt handler registers
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MPUIO control and data registers
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MCSI1 and MCSI2’s MAIN_PARAMETERS_REG registers.
