Coprocessor 15
2-18
Table 2–8. Domain Configuration
Value
Access Type
Description
0b00
No access
Any access generates a domain fault.
0b01
Client
Access rights are checked against the permission given by the page
descriptor.
0b10
Reserved
Behaves like no access
0b11
Manager
The access rights are not checked; permission faults cannot be generated.
Reading CP15 register 5 returns the value of the fault status register (FSR).
The FSR contains the source of the last data fault. Only the bottom 9 bits are
returned. The top 23 bits are unpredictable. The FSR indicates the domain and
type of access being attempted when an abort occurred.
Table 2–9. CP15 Fault Status Register
Bit
Name
Function
31–9
UNP/SB
Reserved: Do not rely on any particular value in these bit locations during a read
(ensure they are masked properly). Write these bits as zero.
8
0
Read as 0.
7–4
Domain
Specify which of the 16 domains (D15 – D0) was being accessed when the last
fault occurred.
3–0
Status
Indicate the type of fault due to the last access being attempted. The encoding of
these bits is shown in Table 2–23, Priority Encoding of the Fault Status Register.
The FSR is only updated for data access faults, not for instruction fetch faults.
When a fault occurs during a load or store multiple (LDM or STM instructions), the
FSR records the domain corresponding to the first fault caused by LDM or STM.
For example, an LDM performing 12 accesses may cross a page boundary with,
say, four accesses in one page and eight in the next page. If accessing the
second page causes an abort, the FSR and FAR record the information related to
the fifth access.
The CRm and opcode_2 fields are SBZ when reading this register. Writing CP15
register 5 sets the fault status register to the value of the data written. The upper
24 bits written are SBZ. The CRm and opcode_2 fields are SBZ when writing to
this register.
