UART/Autobaud Control and Status Registers
12-29
UART Devices
The IIR is a read-only register that provides the source of the interrupt in a
prioritized manner.
Table 12–24. UART Mode Interrupt Identification Register (IIR)
Bit
Name
Value
Function
R/W
Reset
Value
7–6
FCR_MIRROR
Mirror the contents of FCR(0) on both bits
R
00
5–1
IT_TYPE
Priority
5
4
3
2
1
Source
1
0
0
0
1
1
Receiver line status
error
2
0
0
1
1
0
RX time-out
2
0
0
0
1
0
RHR interrupt
3
0
0
0
0
1
THR interrupt
4
0
0
0
0
0
Modem interrupt
5
0
1
0
0
0
Xoff/special character
6
1
0
0
0
0
CTS, RTS, DSR
change state from
active (low) to
inactive (high)
R
00000
0
IT_PENDING
0
An interrupt is pending (nIRQ active).
R
1
1
No interrupt is pending (nIRQ inactive).
The enhanced feature register (EFR) enables or disables enhanced features.
Table 12–25. Enhanced Feature Register (EFR)
Bit
Name
Value
Function
R/W
Reset
Value
7
AUTO_CTS_EN
Automatic CTS enable bit
R/W
0
0
Normal operation
1
Automatic CTS flow control is enabled; that is,
transmission is halted when the CTS pin is
high (inactive).
6
AUTO_RTS_EN
Automatic RTS enable bit
R/W
0
0
Normal operation
1
Automatic RTS flow control is enabled; that is,
RTS pin goes high (inactive) when the
receiver FIFO HALT trigger level, TCR(3:0), is
reached, and goes low (active) when the
receiver FIFO RESTORE transmission trigger
level is reached.
