UART/IrDA Control and Status Registers
12-75
UART Devices
The mode of operation can be programmed by writing to MDR1[2:0]; therefore
the mode definition 1 register (MDR1) must be programmed on start-up after
configuration of the configuration registers (DLL, DLH, LCR
…
). The value of
MDR1[2:0] must not be changed again during normal operation.
Table 12–72. Mode Definition 1 Register (MDR1)
Bit
Name
Value
Function
R/W
Reset
Value
7
FRAME_END_MODE
0
Frame-length method
R/W
0
1
Set EOT bit method
6
–
Reserved
R/W
0
5
SCT
Stores and controls the transmission
R/W
0
0
Starts the SIR transmission as soon as a
value is written to THR
1
Starts the SIR transmission with the control
of ACREG2
4
–
Reserved
R
0
3
IR_SLEEP
0
SIR sleep mode disabled
R/W
0
1
SIR sleep mode enabled
2–0
MODE_SELECT
†
000
UART mode
R/W
111
001
SIR mode
111
Disable UART/default state
All the other values are reserved
† The MODE_SELECT = 0x7 setting disables the UART module by disabling the FIFO and the state machine. It does not gate
the functional clock to the module. The lowest power state is not achieved by setting MODE_SELECT = 0x7, but by putting the
UART into sleep mode. The lowest power state is achieved when in sleep mode witht DLL = 0xFFFF and DLH = 0xFFFF.
