Texas Instruments OMAP5910, Technical Reference Manual

Page: 679 / 1209

LCD Controller Operation
11-13 LCD Controller
Figure 11–8.12 BPP Frame Buffer Memory Organization
Frame Buffer Byte Address 7 0
Base P0[7:0]
Base + 1 Unused P0[11:8]
Base + 2 P1[7:0]
Base + 3 Unused P1[11:8]
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Figure 11–9.16 BPP Frame Buffer Memory Organization
Frame Buffer Byte Address 7 0
Base P0[7:0]
Base + 1 P0[15:8]
Base + 2 P1[7:0]
Base + 3 P1[15:8]
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•
•
The OMAP5910 MPU operates in little endian mode and the number and posi-
tion of pixels in an access depend on access type (byte, half-word, or word).
For example, if the LCD controller is in 2 BPP mode and the MPU performs
a read at the beginning of the frame buffer, the result of the read is:
Byte access (8-bit read):
P0 P1 P2 P3
Half-word access (16-bit read):
P4 P5 P6 P7 P0 P1 P2 P3
Word access (32-bit read):
P12 P13 P14 P15 P8 P9 P10 P11 P4 P5 P6 P7 P0 P1 P2 P3