I/O Signals
A-5
Input/Output Descriptions
Table A–1. Input and Output Signals for the OMAP5910 Device (Continued)
Signals
Ballout
Description
SDRAM (continued)
SDRAM.CKE
SDRAM power down control signal
D9
SDRAM.CLK
SDRAM clock
C9
SDRAM.CAS
SDRAM column address srtobe
H9
SDRAM.BA[1]
SDRAM bank select 1
D10
SDRAM.BA[0]
SDRAM bank select 0
C10
SDRAM.A[12]
SDRAM address bit 12
G10
SDRAM.A[11]
SDRAM address bit 11
H10
SDRAM.A[10]
SDRAM address bit 10
C11
SDRAM.A[9]
SDRAM address bit 9
D11
SDRAM.A[8]
SDRAM address bit 8
G11
SDRAM.A[7]
SDRAM address bit 7
C12
SDRAM.A[6]
SDRAM address bit 6
D12
SDRAM.A[5]
SDRAM address bit 5
H11
SDRAM.A[4]
SDRAM address bit 4
C13
SDRAM.A[3]
SDRAM address bit 3
D13
SDRAM.A[2]
SDRAM address bit 2
G12
SDRAM.A[1]
SDRAM address bit 1
C14
SDRAM.A[0]
SDRAM address bit 0
B14
LCD Interface
LCD.VS
LCD vertical synchronization
D14
LCD.HS
LCD horizental synchronization
H12
LCD.AC
LCD ac-bias or output enable for connection to LCD
B15
LCD.PCLK
LCD pixel clock
C15
LCD.P[15]
LCD pixel data bit 15
D15
LCD.P[14]
LCD pixel data bit 14
C16
LCD.P[13]
LCD pixel data bit 13
A17
