Power Management
15-32
The DPLL idle control logic receives signals from clock generation modules,
indicating when the output clock can be stopped. The DPLL idle mode is en-
tered when the IDLDPLL_ARM bits in the MPU idle mode entry 1 register
(ARM_IDLECT1) are set to logic 1.
15.3.4 Chip Idle and Wake-Up Control
In the status request register (STATUS_REQ_REG), both the CHIP_IDLE and
WAKEUP_nREQ signals can be used by the ULPD idle logic to control the in-
put clock source. The CHIP_IDLE signal remains high until the DPLLs ac-
knowledge that they have entered the IDLE mode. The WAKEUP_nREQ sig-
nal goes active as soon as one of the chip wake-up conditions occurs (MPU
or DSP interrupt, DMA request, local bus activity). The CHIP_IDLE signal can
be used by the ULPD to decide when to stop CLKIN (CK_REF) to the clock
generation module, and it uses the WAKEUP_nREQ signal to restart the clock
(see Figure 15–13).
Figure 15–13. Chip Idle and Wake-Up Control
External clock
requests
ULPD
sleep mode
state machine
Internal clock
request
CHIP_IDLE
WAKEUP_nREQ
CHIP_nWAKEUP
IRQs and
interrupts
Clock
management
chip idle and
wakeup control
SDCLK_EN
SDRAM clock
enable
NFRP
flash power
down
Power-on reset
DSP_IDLE
MPU_IDLE
TCLB_EN
In the status request register (STATUS_REQ_REG), the following signals are
used in chip idle and wake-up control:
-
CHIP_nWAKEUP: CHIP_nWAKEUP is the acknowledge of ULPD when
CHIP_IDLE signal is active. It indicates to the clock management module
that the ULPD has left the awake mode and the 12-MHz clock, CLKIN, is
off.
-
When CHIP_IDLE becomes inactive, the ULPD the releases CHIP_nWA-
KEUP signal to indicate that the ULPD is in awake mode and CLKIN is
back on. This signal provides the ULPD with more control of the
OMAP5910 device wake up.
