Watchdog Timer
8-11
DSP Private Peripherals
Table 8–14. PTV Divisors: Watchdog Timer
PTV
Divisor
0
2
1
4
2
8
3
16
4
32
5
64
6
128
7
256
The timer period is defined by:
-
The value of the PTV, which is forced to 7 if the timer is in watchdog mode
-
The value of the load register
The timer interrupts period is:
t
int
=t
clk
X (LO 1) x 2
(PTV+1)
where t
clk
is the clock period of the input clock.
Table 8–15 shows the characteristics of the watchdog timer for different input
frequencies:
Table 8–15. Watchdog Timer Characteristics
Input Clock
t
clk
, Clock Period
†
LOAD_TIM
t
int
, Timer Interrupt Period, PTV = 7
12 MHz
1167 ns
0001
597.34
µ
s
12 MHz
1167 ns
FFFF (max interrupt period)
19.57 s
† The 12-MHz clock is divided by 14.
If LOAD_TIM = 0 and AR (auto-reload mode) = 1, the timer is always 0 and can
never decrement. Here the timer interrupt is asserted and stays asserted all
the time. Since the timer interrupts are edge-senditive, only one interrupt is
recognized because there is one initial edge, and then the interrupt is asserted
constantly.
