Texas Instruments OMAP5910, Technical Reference Manual

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OMAP5910 Local Bus MMU
14-105 Universal Serial Bus Host
Table 14–52. LB MMU Fault Address Low Register (LB_MMU_FAULT_AD_L_REG)
Access
Hardware
Reset
Bit Name Function
User Sup
Reset
Value
15–0 Fault_address_LSB Least significant 16 bits of the local
bus address that caused a local bus
MMU fault R R 0x0000
The LB MMU fault status register provides information on the type of fault
encountered at the last local bus MMU fault.
Table 14–53. LB MMU Fault Status Register (LB_MMU_FAULT_ST_REG)
Access
Hardware
Reset
Bit Name Function
User Sup
Reset
Value
15–3 Reserved Reserved - - -
2 Perm_fault Permission fault. Active high R R 0
1 Tlb_miss TLB miss (when WTB disabled). Active
high R R 0
0 Trans_fault Translation fault (invalid descriptor).
Active high R R 0
The LB MMU register is used to acknowledge the local bus MMU interrupt at
the local bus MMU interrupt generator. Acknowledging the interrupt at the local
bus MMU interrupt generator causes the generator to deassert its interrupt
indication.
In response to a local bus MMU interrupt, the interrupt service routine must:
1) Read LB_MMU_FAULT_AD_L_REG and LB_MMU_FAULT_AD_H_REG.
2) Read LB_MMU_FAULT_ST_REG.
3) Determine how to respond to the faulty access.
4) Acknowledge the interrupt by writing a 1 to LB_MMU_IT_ACK_REG.
5) Acknowledge the interrupt at MPU level 1 interrupt handler IRQ17.