Index
Index-14
MPU public peripherals (continued)
camera interface
DMA procedure
FIFO buffer
interrupt generator
overview
registers
set of order
clock
divider
switching
data validation
DMA procedure
event capture
FOSCMOD
HDQ, description
horizontal/vertical signal ports
image data ports
MicroWire interface
protocol
registers
MPU I/O
GPIO event capture
GPIO interrupt masking
overview
real time clock
scalable time-tick interrupt
set of order
MPU/DSP
communication
shared peripherals
GPIOs
overview
MPUI
access modes
endianism conversion
features
mu-law interface
See MCSI1, MCSI2
multichannel
enable, MCSI
frame structure
serial interface
See MCSI
multiplexing, conflicts
N
NAK
See non-acknowledged
noise, filter, I2C prescaler
non-acknowledged, transaction
OUT
USB IN
not ready, EMIFS functionality
null pointers
O
OHCI
controller, overview
data buffers, and endianism
differences from OMAP1510
interrupts
null pointers
OMAP1510 implementation
reset, USB host controller
OMAP1510
289-pin package, diagram
architecture
clock management, defined
description
device identification
die identification
elastic buffering
enabling
features
mailboxes
memory interfaces
MPU memory map
OMAP1509 compatibility
overview
pin multiplexing, generic
pulldown, control
pullup, control
software, compatibility
SRAM memory, defined
traffic controller, defined
transceiverless link logic
onchip memory, DSP subsystem, CPU
overview
operating system, scheduling, Microsoft Windows
CE