MPU TI Peripheral Bus Bridges
2-69
MPU Subsystem
Table 2–63. MPU TIPB Control Register (MPU_TIPB_CNTL_REG) – Offset: x08
Bit
Value
Description
Size
Access
Reset
Value
1
1
Write buffer is enabled for strobe domain 1.
1
R/W
0
0
Write buffer is bypassed.
0
1
Write buffer is enabled for strobe domain 0.
1
R/W
0
0
Write buffer is bypassed.
Table 2–64. Enhanced TIPB Control Register (ENHANCED_TIPB_CNTL) – Offset: x0C
Bit
Description
Size
Access
Reset
Value
3
When low, a tc_abort interrupt is sent back to the MPU, when
MPU TIPB access is timed out.
1
R/W
1
2
When high, incoming signals from MPU and DMA are clocked.
Used when running at high frequency.
1
R/W
1
1
When low, an interrupt is sent to the MPU when a TIPB write
access is aborted or when any TIPB access has a size mismatch.
When high, the interrupt is masked.
1
R/W
1
0
A value of 1 enables the time-out feature.
1
R/W
1
Table 2–65. Address Debug Register (ADDRESS_DBG) – Offset: x10
Bit
Description
Size
Access
Reset
Value
15–0
Address from MPU memory interface saved on abort or ac-
cess size mismatch
16
R
0xFFFF
Table 2–66. Data Debug Register LSB (DATA_DEBUG_LOW) – Offset: x14
Bit
Description
Size
Access
Reset
Value
15–0
Bytes 15–0 of data bus from MPU
16
R
0xFFF
