Clock Generation and Reset Control Registers
15-52
Table 15–6. MPU Clock Control Register (ARM_CKCTL) (Continued)
Bit
Reset
Value
Type
Description
Value
Name
13
EN_DSPCK
This bit allows turning on DSP_CK while DSP is
still in a reset state.
R/W
1
0
Disable DSP_CK to be turned off during reset
state.
1
Enable DSP_CK to be turned on during reset
state.
12
ARM_TIMXO
Selects either CK_GEN1 or input reference clock
(CLKIN) to supply internal MPU timers.
R/W
1
0
The ARMTIM_CK clock frequency is input
reference clock.
1
ARMTIM_CK frequency is issued from
CK_GEN1.
11–10
DSPMMUDIV (1:0)
These read/write bits define prescaler value from
frequency of CK_GEN2 to DSPMMU clock
domain clock (DSPMMU_CK).
R/W
0
9–8
TCDIV (1:0)
These read/write bits define prescaler value from
frequency of CK_GEN3 to TC clock domain
clock (TC_CK).
R/W
0
7–6
DSPDIV (1:0)
These read/write bits define prescaler value from
frequency of CK_GEN2 to DSP clock domain
clock (DSP_CK).
R/W
0
5–4
ARMDIV (1:0)
These read/write bits define prescaler value from
frequency of CK_GEN1 to MPU clock domain
clock (ARM_CK).
R/W
0
Note:
If you select the fully synchronous mode, then it is your responsibility to program the divide-down bits so that ARMDIV,
DSPDIV DSPMMUDIV, and TCDIV are all equal. At reset, these divide-down bits are all defaulted to divide by 1.
In any mode, the DSPDIV and DSPMMUDIV must be set so that the DSPMMU_CK is either = to DSP_CK or
DSP_CK/2.
In synchronous scalable mode, you must make sure that the DSPMMUDIV and ARMDIV are greater than or equal to
TCDIV.
