Inter-Integrated Circuit Controller
7-61
MPU Public Peripherals
Figure 7–27. I
2
C Data Transfer Formats
S
S
Slave Address
R/W
ACK
Data
ACK
Data
ACK
S
1
7
1
1
8
1
8
1
1
S
Slave Address 1st 7-Bit
R/W
ACK
ACK
Data
ACK
S
1
7
1
1
8
1
8
1
1
(a) 7-Bit Addressing Format
Slave Address 2nd 7-Bit
1 1 1 1 0 X X
0
(Write)
(b) 10-Bit Addressing Format
S
Slave Address
R/W
ACK
Data
ACK
S
1
7
1
1
8
1
1
ACK
1
1
Slave Address
7
R/W
ACK
1
8
Data
Any Number
of Bytes
Any Number
of Bytes
(c) Addressing Format With Repeated Start Condition
Master Transmitter
In this mode, data assembled in one of the previously described data formats
is shifted out on the serial data line SDA in synchronism with the self-generated
clock pulses on the serial clock line SCL. The clock pulses are inhibited and
SCL held low when the intervention of the processor is required after a byte
has been transmitted.
Master Receiver
This mode can only be entered from the master transmitter mode. With either
of the address formats (Figure 7–27 (a), (b), and (c)), the master receiver is
entered after the slave address byte and bit R/W has been transmitted if R/W
is high. Serial data bits received on bus line SDA are shifted in synchronism
with the self-generated clock pulses on SCL. The clock pulses are inhibited
and SCL held low when the intervention of the processor is required after
a byte has been transmitted. At the end of a transfer, it generates the stop
condition.
Slave Transmitter
This mode can only be entered from the slave receiver mode. With either of
the address formats (Figure 7–27 (a), (b), and (c)), the slave transmitter is
entered if the slave address byte is the same as its own address and bit R/W
has been transmitted if R/W is high. The slave transmitter shifts the serial data
