Clock Generation and Reset Control Registers
15-68
The DSP reset control 2 register (DSP_RSTCT2) sets the PER_EN signal that
resets peripherals attached to the DSP.
Table 15–22. DSP Reset Control 2 Register (DSP_RSTCT2) – Offset Address: 0x14
Bit
Name
Value
Description
Type
Reset
Value
15–1
RESERVED
Reading these bits gives undefined values. Writing to
them has no effect.
0
PER_EN
This read/write bit controls the DSPPER_nRST signal
that can be used to reset and/or enable peripherals
connected to the DSP.
R/W
0
0
Writing a logic 0 sets DSPPER_nRST signal to active.
1
Writing a logic 1 sets DSPPER_nRST signal to inactive.
The DSP system status register (DSP_SYSST) contains the system
information.
Table 15–23. DSP System Status Register (DSP_SYSST) – Offset Address: 0x18
Bit
Name
Value
Description
Type
Reset
Value
15–14 RESERVED
Reading these bits gives undefined values. Writing to
them has no effect.
13–11 CLOCK_SELECT
(2–0)
These read-only bits reflect CLOCK_SELECT and
indicate current clocking scheme selection.
R
0
10–7
RESERVED
6
IDLE_ARM
This read-only bit indicates MPU state.
R
0
0
MPU active
1
MPU in idle state
Notes:
1) This bit is only to be used for test/debug purposes only.
2) In the OMAP5910 device, the DSP_EN and ARM_RST bits (located in ARM_RSTCT1) must be set together to
activate the global software reset. Setting the SW_RST bit only (DSP_RSTCT1) results in global software reset
flag.
