R&S RTO6, Руководство пользователя

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Jitter analysis and clock data recovery
R&S
®
RTO6
1118 User Manual 1801.6687.02 ─ 05
Remote command:
CDR:HARDware:BREStimate
on page 2516
Sampling time
Sets a sampling time for the clock signal, an offset for the clock edge in relation to the
bit start. The clock edge sets the beginning of the unit interval. The sampling time is a
number between 0 and 1. Value 0 sets the clock edge to the beginning of the bit
period; value 0.5 sets the clock edge to the middle of the bit period.
Remote command:
CDR:HARDware:SAMTime
on page 2517
PLL settings
Phase-locked loop parameters are listed below.
Note : Nomial bit rate, bandwidth and relative bandwidth are interacting settings. Modi-
fying one parameter also changes one of the dependent parameters.
"Bandwidth" Sets the PLL bandwidth. It defines the part of the spectrum that the
PLL can follow during synchronization. The PLL bandwidth is usually
defined by the transmission standard.
"Rel. band-
width" Sets the relative bandwidth, that is the ratio of the nominal bit rate to
the PLL bandwidth.
"Order" Sets the order of the PLL: first or second order. PLL of higher order
can compensate for more complex jitter behavior.
"Damping" Sets the damping factor, which is only relevant for second order PLL.
Remote command:
CDR:HARDware:PLL:ORDer
on page 2516
CDR:HARDware:PLL:BWIDth
on page 2517
CDR:HARDware:PLL:RELBwidth
on page 2517
CDR:HARDware:PLL:DAMPing
on page 2517
18.3.2.2 CDR trigger
The CDR triggers on the edges of the clock that is recovered from a data signal by the
hardware CDR. The CDR trigger is the prerequisite for correct eye formation, and thus
for correct jitter measurements and statistics.
The trigger point corresponds to the clock edge that indicates the bit start, and it con-
siders the UI offset.
Access: directly from the hardware CDR setup, or "Menu" > "Trigger" > "Setup" tab >
"Type" =
CDR
Clock data recovery