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Out-of-Step Protection (ANSI 78)
141
7UM62 Manual
C53000-G1176-C149-3
Figure 2-68 shows the logic diagram of the out-of-step protection. The feature has two
stages and can be blocked by a binary input.
Figure 2-68
Logic Diagram of the Out-of-Step Protection
U
1
I
1
--------
Z
1
=
U
1
FNo. 05067
Tripping
matrix
&
n=0
n
≥
1
n=n+1 n
≥
n1
3509
Reset
Release
Characteristic 1
Increment
FNo. 05069
FNo. 05071
FNo. 05068
&
n=0
n
≥
1
n=n+1
n
≥
n2
Reset
Release
Characteristic 2
Increment
FNo. 0507
FNo. 05072
U
L1
U
L2
U
L3
I
2
I
L1
I
L2
I
L3
I
1
I
1
>
I
2
<
&
O/S
– Out-of-step signal for the duration of
Ch. 1
– Characteristic 1
Ch. 2
– Characteristic 2
U
1
– Complex positive sequence component of the voltages
I
1
– Complex positive sequence component of the currents
I
2
– Complex negative sequence component of the currents ^
FNo. 05053
FNo. 05062
TMin
TRIP CMD