Shihlin electric SDP Series, Manual

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4.
When the host controller detects that the ABSR is at the high level, it will immediately read
the data on the ABSD. And then set the ABSQ to the high level to notify the drive for data
reading competition.
5.
After the Tn confirmation time, the drive sets ABSR to the low level, and informs the host
controller to prepare communication for the next bit.
6.
When the controller detects that the ABSR is at a low level, it will request the next bit from
the drive.
7.
If the drive has the data ready, the ABSR signal will be enabled.
8.
After Tr communication waiting time, if the controller does not read data and pulls up the
ABSQ signal, ABSW alarm will occur and the communication will stop.
9.
After the controller detects the ABSW communication error, it will set ABSE to the low level
to make it ready for re-communication.
10.
Re-enable ABSE signal and restart the communication.
11.
The controller sets the ABSQ signal to a low level and sends a reading request.
12.
After the Tq confirmation time, the drive will notify the controller that data can be read.
13.
When the controller detects that the ABSR is at the high level, it will immediately read the
data on the ABSD and set the ABSQ to the high level to notify the drive that the data has
been read.
14.
After the Tn confirmation time, the drive sets ABSR to the low level and informs the host
controller that it can prepare for the communication of next bit.
15.
When the host controller detects that the ABSR is at a low level, it will request the next bit
from the drive. Repeat step 11 ~ step 14 to complete data communication of a total of 80
bits from 0 to 79.