7-19
MB86R02 ‘Jade-D’ Hardware Manual V1.64
7.4.12 Multiplex mode setting register (CMUX_MD)
Address
FFF 30h
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
(Reserved)
CMPX_
MODE
11
CMPX_MODE10 CMPX_MODE9
CMPX_
MODE8
CMPX_
MODE7
CMPX_
MODE6
CMPX_
MODE4
CMPX_MODE3
CMPX_MODE2
R/W
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value 0
0
0
1
1
0
0
1
0
1
0
0
0
1
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
(Reserved)
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Initial value 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit field
Function
Number
Name
31-29
(Reserved)
Reserved
Writes are ignored. Reads will return a '0' at all times.
28
CMPX_MODE_11
Selects the first or second function pin multiplex function of pin multiplex table 11 (see Overview
chapter). Selects SPI master interface 0 or GPIO[23:20].
0
SPI master IF 0 is available at external Pins
1
GPIO[23:20] is available at eternal Pins (CMPX_MODE2[1]
must be ‘0’) (initial value)
27-26
CMPX_MODE_10
Selects the first, second or third pin multiplex function of pin multiplex table 10 (see Overview
chapter). Selects (UART 1, UART2, SPI master interface 1) or (GPIO[19:16], SPI master
interface 1) or SD interface.
00
Serial input and serial output of UART1 and UART2
and SPI master IF 1 available
01
GPIO16-19 instead of UART1 and UART2, keep SPI
master IF 1
10
SD-Card IF available (initial value)
25-24
CMPX_MODE_9
Selects the first, second or third pin multiplex function of pin multiplex table 2 (see Overview
chapter).
00
Serial input, serial output and flow control signals CTS
and RTS of UART0 available
01
GPIO15-12 instead of UART0 available (initial value)
10
Serial input and serial output of UART0 and UART3
are available
Summary of Contents for MB86R02
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Page 497: ...18 139 MB86R02 Jade D Hardware Manual V1 64 VSYNC is output 1 dot clock faster than HSYNC ...
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