Fujitsu MB86R02, Hardware Manual

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13-2
MB86R02 ‘Jade-D’ Hardware Manual V1.64
13.4 Block Diagram
Figure 13-1 shows block diagram of DDR2 controller (DDR2C.)
AXI IF
with
arbiter
FIFO
address
DRAM IF
DDRIF
Macro
Write address channel
Write data channel
Write response channel
Read address channel
Read data channel
FIFO
Read data
Control signal
AHB IF
Add
RData
WData
SSTL_18
I/O
operation
166MHz
operation
83MHz
AXI RESET
AHB RESET
FIFO
write Data
AXI IF
FIFO
Read control
DDR2SDRAM
IF
ODTCONT
VREF0/1
OCD/ODT
AHB IF
( Register)
Figure 13-1 Block diagram of DDR2 controller (DDR2C)
Block Function
AHB IF
•
Slave function of AHB IF
•
Control register.
AXI IF
•
Slave function of AXI IF
•
FIFO control function
FIFO
•
Address/Write
•
Data/Read
•
Control/Read
•
Data storage FIFO
DRAM IF
•
DDRIF macro control function
•
SDRAM IF control function
DDRIF macro
•
Connection between DRAM IF module and IO (Read data’s importing phase
adjustment)
•
Built-in DLL
SSTL_18 I/O
•
STUB series terminated logic for 1.8V single end buffer (OCD and ODT functions
are embedded)
•
STUB series terminated logic for 1.8V differential buffer (OCD and ODT functions
are embedded)
•
ODT auto. adjustment function
Table 13-1 Individual block function