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MB86R02 ‘Jade-D’ Hardware Manual V1.64
TIS (Tile Size)
Register
address
DrawBaseA 468
H
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
TISN
TISM
R/W
RW
RW
Initial value
1000000
1000000
This register specifies the tile size (m, n).
Bit 6 to 0
TISM (Title Size M)
Sets horizontal tile size. Any power of 2 between 4 and 64 can be used. Values that are
not a power of 2 cannot be used.
0.000100
M=4
0001000
M=8
0010000
M=16
0100000
M=32
1000000
M=64
Other than
the above
Setting disabled
Bit 22 to 16
TISN (Title Size N)
Sets vertical tile size. Any power of 2 between 4 and 64 can be used. Values that are not
a power of 2 cannot be used.
0000100
N=4
0001000
N=8
0010000
N=16
0100000
N=32
1000000
N=64
Other than
the above
Setting disabled
TOA (Texture Buffer Offset address)
Register
address
DrawBaseA 46C
H
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
XBO
R/W
RW
Initial value
Don’t care
This register sets the texture buffer offset address. Using this offset value, texture patterns can be
referred to the texture buffer memory.
Specify the word-aligned byte address (16 bits). (Bit 0 is always “0”.)
Summary of Contents for MB86R02
Page 24: ...MB86R02 Jade D Hardware Manual V1 64 ...
Page 76: ...3 2 MB86R02 Jade D Hardware Manual V1 64 Figure 3 1 Memory map 1 ...
Page 77: ...3 3 MB86R02 Jade D Hardware Manual V1 64 Figure 3 2 Memory map 2 ...
Page 167: ...8 8 MB86R02 Jade D Hardware Manual V1 64 ...
Page 214: ...11 7 MB86R02 Jade D Hardware Manual V1 64 15 16 cycles initial value ...
Page 497: ...18 139 MB86R02 Jade D Hardware Manual V1 64 VSYNC is output 1 dot clock faster than HSYNC ...
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Page 682: ...22 2 MB86R02 Jade D Hardware Manual V1 00 FUJITSU PROPRIETARY AND CONFIDENTIAL ...
Page 811: ...29 24 MB86R02 Jade D Hardware Manual V1 64 ...