Fujitsu MB86R02, Hardware Manual

Page: 277 / 892

15-14
MB86R02 ‘Jade-D’ Hardware Manual V1.64
15.6.5 DMAC source address register (DMACSAx)
Address
ch0
：
FF18 (h) ch1
：
FF28 (h) ch2
：
FF38 (h) ch3
：
FF48 (h)
ch4
：
FF58 (h) ch5
：
FF68 (h) ch6
：
FF78 (h) ch7
：
FF88 (h)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DMACSA[31:16]
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DMACSA[15:0]
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit field
Description
No. Name
31-0 DMACSA[31:0]
(DMAC Source
Address)
These bits are used to specify source address to start DMA transfer, and they are able to
be read during DMA transfer.
When fixed address function (DMACB/FS) is disabled, these bits are incremented
according to the transfer width (DMACB/TB) after completing source address properly.
After the DMA transfer, DMAC sets the next source address to these bits.
[Note]
It is prohibited to set DMAC register address to DMACSA.
DMACSA Function
x(h) Source address to start DMA transfer
(Initial value: 32'h00000000)