MB86R02 ‘Jade-D’ Hardware Manual V1.64
22-40
RSCK (pin DISP[j])
Register DIR_Pin_ctrl[j].Delay=0
RSCKH
RSCKL
50%
RSDAT (pins DISP[i])
Registers DIR_Pin_ctrl[i].Delay=1
RSHD
RSSU
RSHD
RSSU
0V diff.
Pins TSIG[i]
Register Dir_SSwitch.SSwitch =0
TSIGHD
TSIGSU
TTL
diff.
Figure 22-9 RSDS operation Output Timing
Figure 22-10 Rise Fall Times
Summary of Contents for MB86R02
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Page 76: ...3 2 MB86R02 Jade D Hardware Manual V1 64 Figure 3 1 Memory map 1 ...
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Page 497: ...18 139 MB86R02 Jade D Hardware Manual V1 64 VSYNC is output 1 dot clock faster than HSYNC ...
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