Fujitsu MB86R02, Hardware Manual

Page: 191 / 892

9-23
MB86R02 ‘Jade-D’ Hardware Manual V1.64
9.5.10 IRQ test register (IRQTEST)
The IRQTEST register tests interrupt controller's IRQ interrupt function.
When the ITEST bit of the FIQTEST register is "1", this register becomes valid.
Set "0" to each bit of the IRQTEST register.
Address
IRC0:
FFFF_FE00
H
or FFFE_8000
H
+ 24
H
IRC1: FFFB_0000
H
+ 24
H
IRC2: FFFB_1000
H
+ 24
H
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name ITST31 ITST30 ITST29 ITST28 ITST27 ITST26 ITST25 ITST24 ITST23 ITST22 ITST21 ITST20 ITST19 ITST18 ITST19 ITST36
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name ITST15 ITST14 ITST13 ITST12 ITST11 ITST10 ITST9 ITST8 ITST7 ITST6 ITST5 ITST4 ITST3 ITST2 ITST1 ITST0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit field
Explanation
Number Name
31-4 ITST31-0 It is a control bit to test interrupt controller's IRQ interrupt function.
0 The interrupt is not generated.
1 The interrupt corresponding to IRQ is generated.
Set "0" to these bits.
Each bit is initialized by reset by "0".