Fujitsu MB86R02, Hardware Manual

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27-8
MB86R02 ‘Jade-D’ Hardware Manual V1.64
27.6.5 I2SxCNTREG register
Address ch0
：
FFEE_0008 (h)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CKRT OVHD
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name – MSKB MSMD SBFN RHLL ECKM BEXT FRUN MLSB TXDIS RXDIS SMPL CPOL FSPH FSLN FSPL
R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0
Bit field
Description
No. Name
31-26 CKRT[5:0] This sets output clock frequency dividing ratio at master operation.
AHB clock is divided at ECKM = 0, and external clock is divided at ECKM = 1. Only
even number of the ratio is supported and output clock's DUTY becomes 50%. CKRT
[5:0]
×
2 becomes number of AHB clock or external clock cycle included in 1 cycle
(I2S_SCKx.)
Setting examples are shown below.
External clock mode and external clock are 24.576MHz:
CKRT Dividing
ratio
I2S_SCKx
0x00 By pass
24.576MHz
(external clock is output as it is)
0x01 1/2 12.288MHz
0x02 1/4 6.144MHz
0x03 1/6 4.096MHz
0x04 1/8 3.072MHz
0x05 1/10 2.458MHz
: : :
Internal clock mode and AHB clock are 80MHz:
CKRT Dividing
ratio
I2S_SCKx
: : :
0x04 1/8 10MHz
0x05 1/10 8MHz
0x06 1/12 6.67MHz
0x07 1/14 5,71MHz
0x08 1/16 5MHz
0x09 1/18 4.44MHz
: : :
25-16 OVHD[9:0] Frame rate is able to be adjusted by inserting OVHD bit following to valid data of the
frame. OVHD section of the transmission frame becomes in high impedance. Up to 0
– 1023 OVHD bit is able to be inserted, and is inserted at the end of the frame.
The value set to OVHD becomes the number of insertion bit.
The following expressions are formed for OVHD and frame synchronous signal cycle
(2nd.)
1 sub frame construction:
OVHD = Frame synchronous signal cycle/I2S_SCKx cycle – (S0CHL + 1)
×
(S0CHN + 1)
2 sub frame construction:
OVHD = Frame synchronous signal cycle/I2S_SCKx cycle – (S0CHL + 1)
×
(S0CHN + 1)
– (S1CHL + 1)
×
(S1CHN + 1)