Fujitsu MB86R02, Hardware Manual

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15-8
MB86R02 ‘Jade-D’ Hardware Manual V1.64
15.6.3 DMA configuration A register (DMACAx)
Address
ch0
：
FF10 (h) ch1
：
FF20 (h) ch2
：
FF30 (h) ch3
：
FF40 (h)
ch4
：
FF50 (h) ch5
：
FF60 (h) ch6
：
FF70 (h) ch7
：
FF80 (h)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name EB PB ST IS[4:0] BT[3:0] BC[3:0]
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TC[15:0]
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit field
Description
No. Name
31 EB
(Enable Bit)
This bit is used to control DMA channel transfer.
When "1" is set to this bit, channel waits for the trigger to start DMA transfer (DMACR/DE
bits should be set to "1" beforehand.)
DMAC sets "0" to this bit after DMA transfer, then this channel is disabled and DMA
transfer is not performed until "1" is set to this bit. If "0" is set to this bit during DMA
transfer, DMA stops at transfer gap which is regarded as forcible termination.
Refer to DMACR/DE bits description for transfer gap.
This bit is able to use for resetting each configuration register of the channel during DMA
transfer.
0 This channel is disabled (initial value)
1 This channel is enabled
30 PB
(Pause Bit)
This bit is used to discontinue DMA channel transfer.
When "1" is set to this bit, this channel stops the transfer, and it is not performed until this
bit is cleared.
If "1" is set to this bit during DMA transfer, DMA stops at transfer gap. Refer to
DMACR/DE bits description for transfer gap.
When "1" is set to this bit before receiving transfer request to acquire bus right, DMAC is
immediately paused; in this case, DMAC does not hold transfer request during the
pause.
When "0" is set to this bit during DMA transfer is in pause, it is cleared and DMAC waits
for new transfer request.
This bit is able to be used to stop DMA transfer without resetting each configuration
register of the channel.
0 Initial value
1 This channel is stopped