Fujitsu MB86R02, Hardware Manual

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5-19
MB86R02 ‘Jade-D’ Hardware Manual V1.64
Bit field
Description
No. Name
8 PLLRDY PLLREADY monitoring
This bit monitors internal signal, PLLREADY with external pin CLK clock.
The PLLREADY signal shows overflow of the value selected at LUMMODE[1:0] bit by
the timer which calculates PLL oscillation stabilization waiting time.
0 PLLREADY signal is "low" (initial value)
1 PLLREADY signal is "high"
Write access to this bit is ignored.
7 PLLBYPASS PLL bypass mode
This bit bypasses PLL.
0 PLL clock is used.
1 PLL is bypassed
Note: Do not change PLLBYPASS bit and PLLMODE[4:0] at the same time since clock
switch of both external pin CLK and PLL clocks needs to be changed. If they are
changed at the same time, CRG detects PLL oscillation frequency change and
state becomes PLL oscillation stabilization waiting before PLL bypass mode.
Reference: The initial value of this bit is settable with setting external pin, PLLBYPASS.
6-5 LUWMODE[1:0] PLL locked waiting mode
These bits are used to set PLL oscillation stabilization wait time.
00 T
CLK
×
(2
n0
- 2
m
+ 1)
01 T
CLK
×
(2
n1
- 2
m
+ 1)
10 T
CLK
×
(2
n2
- 2
m
+ 1) (initial value)
11 T
CLK
×
(2
n3
- 2
m
+ 1)
T
CLK
: Cycle time of CLK reference clock
n0 = 11
n1 = 12
n2 = 13
n3 = 14
m = 8
The wait time depends on CLK cycle time and PLL lock-up time, moreover it does
not need to be changed from the initial value.