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Fujitsu MB86R02, Hardware Manual

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15-17 

MB86R02 ‘Jade-D’ Hardware Manual V1.64 
 

 

Restrictions 

When DMA transfer is performed by an external (DREQ) or peripheral (IDREQ) request, there 
are restrictions for external and peripheral signal pins.    

 

 

1.

 DREQ/IDREQ 

DREQ/IDREQ must be asserted for at least 2 cycles of the AHB clock 

(

HCLK). 

There is no restriction for the timing of negating DREQ/IDREQ.   

 

After asserting DACK/IDACK, DMAC is able to accept new a transfer request (edge of 
DREQ/IDREQ) for the next DMA transfer. 

 

 

2.

 DACK/IDACK 

After the DMAC transfers data to the destination address, DACK/IDACK are asserted for 1 
cycle of the AHB clock (HCLK). If access to the destination is executed correctly, this signal 
is asserted. If destination issues, error, retry or split responses occur on the AHB, it is not 
asserted.

 

 
In block transfer mode, these signals indicate that the DMAC has correctly performed 
destination access.   

 

3.

 DEOP (Data End Operation)/IDEOP 

Basically, DEOP/IDEOP is asserted for 1 AHB clock (HCLK) cycle if the DMAC terminates 
DMA transfer properly or abnormally. Abnormal DMA transfer includes the following cases: 

•

  Forced termination by DSTP/IDSTP   

•

  Forced termination by setting 1'b0 to DMACA/EB   

•

  Reception of an error response from the source/destination 

 

4.

 DSTP (Data Stop)/IDSTP 

DSTP/IDSTP are used to forcibly terminate DMA transfer and asserting them during the 
transfer is permitted (it is also permissible to assert DSTP/IDSTP while DMA data is not 
transferred due to a transfer gap or an interrupt function). 
If these signals are used to forcibly terminate DMA transfer, they are not asserted until 
DEOP/IDEOP are asserted.   

 

5.

 Exceptional operation of DEOP/IDEOP

 

If DSTP/IDSTP are asserted immediately after asserting DREQ/DSTP, the DMAC may 
request the bus to execute an IDLE transfer. In this case, the DMAC may assert 
DEOP/IDEOP for 2 or more cycles of the AHB clock (HCLK).

 

The assertion period of DEOP/IDEOP depends on the number of previous master transfer 
cycles. Figure 15-2 shows an example of this exception operation. 
 

Summary of Contents for MB86R02

Page 1: ...ardware Manual V1 64 MB86R02 Jade D Graphics Controller Hardware Manual Fujitsu Semiconductor Europe GmbH Release 1 64 amended 17 09 2013 13 11 This document is subject to changes and corrections without prior warning ...

Page 2: ...red trademark of ARM Limited in UK USA and Taiwan ARM is a trademark of ARM Limited in Japan and Korea ARM Powered logo is a registered trademark of ARM Limited in Japan UK USA and Taiwan ARM Powered logo is a trademark of ARM Limited in Korea ARM926EJ S and ETM9 are trademarks of ARM Limited System names and the product names which appear in this document are the trademarks of the respective comp...

Page 3: ...e general office use personal use and household use but are not designed developed and manufactured for use accompanying fatal risks or dangers that unless extremely high safety levels are ensured could have a serious effect to the public and could lead directly to death personal injury severe physical damage or other loss i e nuclear reaction control in nuclear facility aircraft flight control ai...

Page 4: ...ect regardless of RX TX usage Corrected GPIO listings number of GPIOs effected with concern to CMPX_MODE_10 descriptions in mulitplex overview and register description Added an additional note concerning multiplex mode 3 if the pins are unused check the table for multiplex mode 3 Corrected 9 6 1 address of instruction vector table to 0000_0080H Corrected IRQ connections diagram in chapter 9 IRQ5 i...

Page 5: ...lmost all tables modified CRG corrected initial value of CRAM register TCON exchanged Figure 22 4 Block diagram of TSIG SSCG updated register description UART changed table 28 2 external input condition CLK 25 0MHz CRIPM 3 0 0001 Addendum differences ES1 ES2 added note about APIX TX initialization V1 30 24 07 2009 von Treuberg CCNT Corrected typo in description of register CAXI_PS ADDENDUM Added n...

Page 6: ...G functional scope ES1 ES2 DMAC I2S added restriction for I2S transfer modes SIG Added new example control flow diagram to 21 6 1 Added new chapter Electrical Characteristics V1 10 18 05 2009 von Treuberg Overview corrected bus connection information added improved overview of multiplex pin groups corrected I2S unit count added section concerning PU PD differences ES1 ES2 updated pin listings unus...

Page 7: ...used pins list Memory Map updated figure CRG Table 5 3 timings updated register descriptions updated for CRPR CRHR CRHB CSEL new registers CRDP0 CRPD1 added CCNT register MBUS2AXU added changed registers CIST CEX_PIN_ST CMSR1 CMSR2 APIX complete register update PWM register update V0 03 12 08 2008 von Treuberg Major changes Preface new block diagram Overview preliminary pinning information multipl...

Page 8: ...dware Manual V1 64 app note for RSDS channel order inversion AC TTL spec change to 42 MHz V0 02 25 05 2007 von Treuberg Reorganization new chapters major alterations of content V0 01 08 03 2007 von Treuberg First version ...

Page 9: ...tures 5 1 5 3 Overview 5 2 5 4 Location in the device 5 3 5 5 Operation 5 3 5 5 1 Reset Generation 5 3 5 5 2 Clock Generation 5 7 5 6 Registers 5 16 5 1 1 Register list 5 16 5 1 2 PLL control register CRPR 5 18 5 1 3 Watchdog timer control register CRWR 5 21 5 1 4 Reset Standby control register CRSR 5 23 5 1 5 Clock divider control register A CRDA 5 25 5 1 6 Clock divider control register B CRDB 5...

Page 10: ...t status mask register CGPIO_ISTM 7 11 7 4 8 GPIO interrupt polarity setting register CGPIO_IP 7 13 7 4 9 GPIO interrupt mode setting register CGPIO_IM 7 13 7 4 10 AXI bus wait cycle set register CAXI_BW 7 15 7 4 11 AXI priority setting register CAXI_PS 7 17 7 4 12 Multiplex mode setting register CMUX_MD 7 19 7 4 13 External pin status register CEX_PIN_ST 7 21 7 4 14 MediaLB set register CMLB 7 22...

Page 11: ...register ICR31 ICR00 9 25 9 6 Operation explanation 9 27 9 6 1 Outline of operation 9 27 9 6 2 Initialization 9 27 9 6 3 Multiple interrupt processing 9 28 9 6 4 Example of IRQ interrupt handler 9 28 9 6 5 Stop and return from sleep mode 9 30 9 6 6 Notes on use of IRC 9 31 10 External Interrupt Controller EXIRC 10 1 10 1 Outline 10 1 10 2 Feature 10 1 10 3 Block diagram 10 2 10 4 Supply clock 10 2...

Page 12: ...1 13 10 13 6 8 DRAM CTRL SET TIME2 register DRCST2 13 12 13 6 9 DRAM CTRL REFRESH register DRCR 13 14 13 6 10 DRAM CTRL FIFO register DRCF 13 15 13 6 11 AXI setting register DRASR 13 16 13 6 12 DRAM IF MACRO SETTING DLL register DRIMSD 13 17 13 6 13 DRAM ODT SETTING register DROS 13 18 13 6 14 IO buffer setting ODT1 DRIBSODT1 13 19 13 6 15 IO buffer setting OCD DRIBSOCD 13 20 13 6 16 IO buffer set...

Page 13: ...Single transfer 15 29 15 7 2 2 Increment and lap transfer 15 30 15 7 3 Channel priority control 15 31 15 7 3 1 Fixed priority 15 31 15 7 3 2 Rotate priority 15 32 15 7 4 Retry split and error 15 33 15 7 4 1 Retry and split 15 33 15 7 4 2 Error 15 34 15 8 DMAC Configuration Examples 15 35 15 8 1 DMA start in Single channel 15 35 15 8 2 DMA start in all channels in demand transfer mode 15 36 16 Host...

Page 14: ... configuration bytes 17 16 17 4 1 RX 17 16 17 4 2 TX 17 26 17 5 GPIO Interface Timing of Sideband Uplink and Downlink 17 38 17 6 Control Flow 17 39 17 6 1 Use cases 17 40 17 6 1 1 Use case 1 17 40 17 6 1 2 Use case 2 17 42 17 6 2 Application Notes for PCB Designers 17 44 18 Graphics Display Controller GDC 18 1 18 1 Preface 18 1 18 2 Features 18 1 18 3 Functional Overview 18 2 18 3 1 Display contro...

Page 15: ...t Signal Control 18 32 18 6 10 4 Output Circuit Example 18 32 18 6 10 5 Display Clock and Timing 18 34 18 6 10 6 Limitations 18 34 18 6 10 7 Dual display configuration example 18 34 18 6 11 Video output limitation 18 35 18 6 12 Interrupt 18 35 18 7 Video Capture 18 37 18 7 1 Video Capture function 18 37 18 7 1 1 Input data Formats 18 37 18 7 1 2 Video Signal Capture 18 37 18 7 1 3 Non interlace Tr...

Page 16: ...mat 18 147 18 9 2 2 Setup processing 18 148 18 9 3 Log Output of Device Coordinates 18 148 18 9 3 1 Log output mode 18 148 18 9 3 2 Log output destination address 18 148 18 9 3 3 Log output format 18 148 18 10 Drawing Processing 18 149 18 10 1 Coordinate System 18 149 18 10 1 1 Drawing coordinates 18 149 18 10 1 2 Texture coordinates 18 150 18 10 1 3 Frame buffer 18 150 18 10 2 Figure Drawing 18 1...

Page 17: ...e Register summary 18 199 18 11 4 1 Drawing Engine register list 18 199 18 11 4 2 Geometry Engine register list 18 206 18 11 5 Drawing control registers 18 207 18 11 6 Drawing mode registers 18 210 18 11 7 Triangle drawing registers 18 228 18 11 8 Line drawing registers 18 231 18 11 9 Pixel drawing registers 18 232 18 11 10 Rectangle drawing registers 18 232 18 11 11 Blt registers 18 233 18 11 12 ...

Page 18: ... 21 3 7 Interrupts For Control Flow 21 2 21 3 8 Programmable Input Picture Source 21 2 21 3 9 Limitations 21 3 21 4 Software Interface 21 3 21 4 1 Format of Register Description 21 3 21 4 2 Global Address 21 4 21 4 3 Register Summary 21 4 21 4 4 Register Description 21 5 21 5 Processing Mode 21 12 21 5 1 Processing Flow 21 12 21 5 2 Processing Algorithm 21 12 21 6 Control Flow 21 13 21 6 1 Example...

Page 19: ...tion Bus Interface 23 2 23 4 3 Interrupt 23 2 23 5 Data Formats 23 3 23 5 1 1 Input Data Format 23 3 23 5 1 2 Output Data Format 23 4 23 6 Software Interface 23 4 23 6 1 Format of Register Description 23 4 23 6 2 Global Address 23 5 23 6 3 Register Summary 23 5 23 6 4 Register Description 23 6 23 7 Processing Mode 23 9 23 7 1 Processing Flow 23 9 23 7 2 Processing Algorithm 23 9 23 7 2 1 Processin...

Page 20: ...pping table 26 3 26 7 Output truth value list 26 3 26 8 Analog pin equivalent circuit 26 4 26 9 Registers 26 5 26 9 1 Register list 26 5 26 9 2 Format of Register Descriptions 26 6 26 9 3 ADCx data register ADCxDATA 26 7 26 9 4 ADCx mode register ADCxMODE 26 7 26 9 5 ADCx power down control register ADCxXPD 26 7 26 9 6 ADCx clock selection register ADCxCKSEL 26 8 26 9 7 ADCx status register ADCxST...

Page 21: ...ister URTxFCR 28 9 28 6 7 Line control register URTxLCR 28 10 28 6 8 Modem control register URTxMCR 28 11 28 6 9 Line status register URTxLSR 28 12 28 6 10 Modem status register URTxMSR 28 13 28 6 11 Divider latch register URTxDLL URTxDLM 28 14 28 7 UART operation 28 16 28 7 1 Example of initial setting 28 16 28 7 2 Example of transfer procedure 28 17 28 7 3 Example of reception procedure 28 18 28...

Page 22: ...ter list 30 4 30 6 2 SPI control register SPInCR 30 6 30 6 3 SPI slave control register SPInSCR 30 8 30 6 4 SPI data register SPInDR 30 11 30 6 5 SPI status register SPInSR 30 12 30 7 Setup procedure flow 30 13 31 CAN Interface CAN 31 1 31 1 Outline 31 1 31 2 Block diagram 31 1 31 3 Supply clock 31 2 31 4 Registers 31 2 32 MediaLB Interface 32 1 32 1 Outline 32 1 32 2 Block diagram 32 1 32 3 Suppl...

Page 23: ... SPI Signal Timing 34 39 34 5 13 CAN Signal Timing 34 40 34 5 14 MediaLB Signal Timing 34 41 34 5 14 1 MediaLB AC Spec Type A 34 41 34 5 14 2 MediaLB AC Spec Type B 34 42 34 5 15 SD Signal Timing 34 44 34 5 15 1 Clock 34 44 34 5 15 2 Input Output Signal 34 44 34 5 16 ETM9 Trace Port Signal Timing 34 46 34 5 17 EXIRC Signal Timing 34 47 34 5 18 Apix Characteristics 34 48 34 5 18 1 Power supply 34 4...

Page 24: ...MB86R02 Jade D Hardware Manual V1 64 ...

Page 25: ...0nm technology CS101 Supply voltage 3 3V I O 1 8V DDR2 1 2V Internal Package Package BGA 484 Extended temperature range 40 105 C CPU core ARM926EJ S core 333 MHz 16KB instruction cache 16KB data cache 16KB Instruction TCM 16KB Data TCM TCM Tightly Coupled Memory ETM9CS Single and JTAG ICE interface Java Acceleration Jazelle technology 8 channel DMA and 2 channel 32 bit timers Operating frequency 3...

Page 26: ...nsible up to 6 channels using I O option GPIO 24 channels APIX I F 2 channels 2x Transmitter or 2x Receiver TCON direct interconnect to column and row drivers via LVTTL or RSDS smart integration panel support smart panel support External Interrupts 4 channels the number of channels of the above IO configuration is tentative Built in SRAM 2x 32k Hardware Run Length Decompression RLD Clock Generatio...

Page 27: ...Hardware Manual V1 64 1 2 Block Diagram The following block diagram provides a top level overview of the device s functional blocks zoom into this PDF document for a detailled view Figure 1 1 MB86R02 Jade D Block Diagram ...

Page 28: ...ging and running a boundary scan GDC core The GDC core consists of a MB86296 Coral PA compatible graphics controller core with two display and capture units The core has two functional modes AHB slave functionality making it possible to write display lists using the CPU core or the DMA controller as a master and AXI master functionality which enables the reading of display lists saved in DDR2 memo...

Page 29: ...logo display MLB MediaLB controller SDMC SD memory controller Host SPI Serial Peripheral Interface SPI is a serial interface for synchronous communication APIX Remote Handler RX TX channels can act as Master or Slave AHB2 bus AHB2 bus 32 bit 83 MHz CCPB Encrypted ROM decoding block DDR2 controller DDR2 controller registers Host SPI Serial Peripheral Interface SPI is a serial interface for synchron...

Page 30: ...S Single and JTAG ICE debugging interface Java acceleration Jazelle technology Bus architecture Multilayer AHB bus architecture ransfer between main memory and each bus master via 64 bit AXI bus Interrupts High speed interrupt 1ch software interrupt Normal interrupt 64ch external interrupt 4ch built in internal interrupt 60ch nterrupt levels are settable by channel Clock PLL multiplication selecta...

Page 31: ...ls dedicated channel 6ch 1 channel capable of input output CTS RTS signals 8 bit pre scaler for baud rate clock generation Enabled DMA transfer I2C 3 3V pin 2ch Supported standard mode max 100kbps high speed mode max 400kbps SPI 2 2ch Full duplex Synchronous transmission Transfer data length 1 bit unit max 32 bit programmable setting The length of the SPI interface packets is variable to permit th...

Page 32: ... control priority and WAIT setting JTAG Compliant to IEIEEE1149 1 IEEE Standard Test Access Port and Boundary Scan Architecture Supports JTAG ICE connection 1 Number of layer of simultaneous display and number of output display as well as capture input for displaying in high resolution may be restricted due to data supply capacity of graphics memory DDR2 controller 2 A part of external pin functio...

Page 33: ...Package Dimensions The package dimensions of the MB86R02 Jade D are shown in the following figure A separate specification possibly containing more detail may be available on the GDC website http www fujitsu com emea services microelectronics gdc ...

Page 34: ...nual V1 64 1 4 Pinning The pin out functionality of the MB86R02 Jade D device is described in this section 1 5 Pin Assignment The following figure shows the pin out assignment of the MB86R02 Jade D Figure 1 3 Pin Assignment top view ...

Page 35: ...1 11 MB86R02 Jade D Hardware Manual V1 64 The following figure shows the pin assignment in functional groups APIX related pins Figure 1 4 Functional Pin Assignment top view ...

Page 36: ...6P R1 15 DISP8P T1 16 DISP10P U1 17 DCLKP V1 18 VSS W1 19 TSG_4 Y1 20 TSG_6 AA1 21 TSG_10 AB1 22 VIN0_4 AC1 23 VIN0_0 AD1 24 CCLK0 AE1 25 VSS AF1 26 VSS AF2 27 CCLK1 AF3 28 VIN1_6 AF4 29 VIN1_4 AF5 30 VIN1_0 AF6 31 MLB_DAT AF7 32 VSS AF8 33 I2S_ECLK AF9 34 CAN_RX1 AF10 35 PWM_O3 AF11 36 HOST_SPI_SCK AF12 37 VPD AF13 38 AVD1 AF14 39 AVS1 AF15 40 DDRTYPE AF16 41 UART_SIN0 AF17 42 UART_SIN1 AF18 43 S...

Page 37: ...KN N26 64 MCKP M26 65 VSS L26 66 MDQSN_2 K26 67 MDQSP_2 J26 68 VSS H26 69 MDQSN_3 G26 70 MDQSP_3 F26 71 VSS E26 72 MEM_ED_3 D26 73 MEM_ED_7 C26 74 MEM_ED_11 B26 75 VSS A26 76 VSS A25 77 VSS A24 78 MEM_EA_1 A23 79 MEM_EA_4 A22 80 MEM_EA_8 A21 81 MEM_EA_12 A20 82 MEM_EA_16 A19 83 MEM_EA_20 A18 84 VSS A17 85 MEM_XRD A16 86 ECLK A15 87 CRIPM0 A14 88 VCM1 A13 89 SDIN1M A12 90 APIXVSS A11 91 XTAL0 A10 9...

Page 38: ... DISP10N U2 116 DCLKN V2 117 VDDE W2 118 GV0 Y2 119 TSG_7 AA2 120 TSG_11 AB2 121 VIN0_5 AC2 122 VIN0_1 AD2 123 VINHSYNC0 AE2 124 VDDE AE3 125 VIN1_7 AE4 126 VIN1_5 AE5 127 VIN1_1 AE6 128 MLB_SIG AE7 129 MLB_CLK AE8 130 VDDE AE9 131 CAN_TX1 AE10 132 PWM_O2 AE11 133 HOST_SPI_DI AE12 134 TESTMODE_3 AE13 135 AD_VRH0 AE14 136 AD_VRH1 AE15 137 TESTMODE_1 AE16 138 UART_SOUT0 AE17 139 UART_SOUT1 AE18 140 ...

Page 39: ... 165 MDQ_31 F25 166 MEM_ED_0 E25 167 MEM_ED_4 D25 168 MEM_ED_8 C25 169 MEM_ED_12 B25 170 MEM_ED_14 B24 171 MEM_ED_15 B23 172 MEM_EA_3 B22 173 MEM_EA_7 B21 174 MEM_EA_11 B20 175 MEM_EA_15 B19 176 MEM_EA_19 B18 177 MEM_EA_23 B17 178 MEM_XWR_1 B16 179 MEM_XCS_4 B15 180 CRIPM1 B14 181 CRIPM3 B13 182 SDIN1P B12 183 APIXVD12 B11 184 XTAL1 B10 185 APIXVD12 B9 186 SDIN0P B8 187 OSC_MODE1 B7 188 RTCK B6 18...

Page 40: ...YNC0 AD4 215 VINFID1 AD5 216 VIN1_2 AD6 217 VINVSYNC1 AD7 218 I2S_SDO AD8 219 I2S_SCK AD9 220 CAN_RX0 AD10 221 PWM_O1 AD11 222 HOST_SPI_DO AD12 223 TESTMODE_2 AD13 224 AD_VIN2 AD14 225 AD_VIN3 AD15 226 TESTMODE_0 AD16 227 UART_XCTS0 AD17 228 UART_SIN2 AD18 229 SPI_SS0 AD19 230 SPI_SS1 AD20 231 I2C_SCL0 AD21 232 INT_A_2 AD22 233 IDLLRST AD23 234 MA_9 AD24 235 MA_6 AC24 236 MA_2 AB24 237 MWE AA24 23...

Page 41: ...EM_XWR_0 C16 264 MEM_XCS_2 C15 265 CRIPM2 C14 266 SVD C13 267 APIXVSS C12 268 OSC_FILTER C11 269 APIXVD33 C10 270 ATST C9 271 APIXVSS C8 272 OSC_BIAS0 C7 273 XSRST C6 274 TESTMODE_4 C5 275 TRACEDATA_3 C4 276 TCK D4 277 TRACECLK E4 278 PLLTDTRST F4 279 DOUTB1_7 G4 280 DOUTG1_5 H4 281 DOUTR1_3 J4 282 DOUTR1_7 K4 283 MPX_MODE_1_0 L4 284 DISP1N M4 285 DISP3N N4 286 DISP5N P4 287 DISP7N R4 288 DISP9N T...

Page 42: ...313 INT_A_3 AC22 314 ODTCONT AC23 315 MA_0 AB23 316 MCS AA23 317 MCAS Y23 318 MDQ_3 W23 319 MDQ_4 V23 320 MDM_0 U23 321 MDQ_11 T23 322 MDQ_12 R23 323 MDQ_14 P23 324 OCD N23 325 ODT M23 326 MDQ_19 L23 327 MDQ_20 K23 328 MDM_2 J23 329 MDQ_27 H23 330 MDQ_25 G23 331 MDQ_30 F23 332 MEM_ED_2 E23 333 MEM_ED_6 D23 334 MEM_ED_10 D22 335 MEM_EA_5 D21 336 MEM_EA_9 D20 337 MEM_EA_13 D19 338 MEM_EA_17 D18 339 ...

Page 43: ...363 VSS T5 364 VSS U5 365 VDDE V5 366 VDDE W5 367 VDD Y5 368 VDD AA5 369 VSS AB5 370 VSS AB6 371 VDDE AB7 372 VDDE AB8 373 VDD AB9 374 VDD AB10 375 VDDE AB11 376 VSS AB12 377 AD_VRL0 AB13 378 AD_VR0 AB14 379 AD_VR1 AB15 380 AD_VRL1 AB16 381 VSS AB17 382 VSS AB18 383 VDDE AB19 384 VDDE AB20 385 VDD AB21 386 VDD AB22 387 DDRVDE AA22 388 DDRVDE Y22 389 VSS W22 390 VSS V22 391 MDQ_6 U22 392 DDRVDE T22...

Page 44: ...D E13 413 PVS E12 414 SDOUT1P E11 415 APIXVSS E10 416 APIXVSS E9 417 SDOUT0P E8 418 JTAGSEL E7 419 VSS E6 420 VSS K10 421 VDD L10 422 VDD M10 423 VDDE N10 424 VDDE P10 425 VDD R10 426 VDD T10 427 VDDE U10 428 VDDE U11 429 VDD U12 430 VDD U13 431 VDDE U14 432 VDDE U15 433 VDD U16 434 VDD U17 435 DDRVDE T17 436 DDRVDE R17 437 VDD P17 438 VDD N17 439 DDRVDE M17 440 DDRVDE L17 441 VDD K17 442 VDD K16 ...

Page 45: ...SS T13 456 VSS T14 457 VSS T15 458 VSS T16 459 VSS R16 460 VSS P16 461 VSS N16 462 VSS M16 463 VSS L16 464 VSS L15 465 VSS L14 466 VSS L13 467 VSS L12 468 VSS M12 469 VSS N12 470 VSS P12 471 VSS R12 472 VSS R13 473 VSS R14 474 VSS R15 475 VSS P15 476 VSS N15 477 VSS M15 478 VSS M14 479 VSS M13 480 VSS N13 481 VSS P13 482 VSS P14 483 VSS N14 484 VSS ...

Page 46: ...ex mode 1 Dependancies setting of register MPX_MODE_1 1 0 First MUX Function Pins related to Capture0 Capture1 Second MUX Function Pins related to Capture0 Capture1 Third MUX Function Pins related to external bus 32 bit interface Pin multiplex mode 2 Dependancies setting of registers CMPX_MODE_9 1 0 and CMPX_MODE_2 1 0 and MPX_MODE_5 1 First MUX Function Pins related to UART0 Second MUX Function P...

Page 47: ...unction Pins related to PWM0 1 2 3 Second MUX Function Pins related to UART4 5 Pin multiplex mode 8 Dependancies setting of registers CMPX_MODE_8 0 and CMPX_MODE_2 1 0 First MUX Function Pins related to SPI Host Second MUX Function Pins related to GPIO8 9 10 11 Pin multiplex mode 9 Does not exist Pin multiplex mode 10 Dependancies setting of registers CMPX_MODE_10 1 0 and CMPX_MODE_2 1 0 First MUX...

Page 48: ...gurable by register CMPX_MODE_4 0 MPXTABLE5 Function fixed after bootup UART0 but other functions still configurable by register CMPX_MODE_9 1 0 CMPX_MODE_2 1 0 MPX_TABLE9 Configurable by register software action ES1 ES2 Modification extension ES1 ES2 CONST0 Drives 0 constantly to this pin Note The first column of each of the following tables is the default state If a non specified mode is selecte...

Page 49: ...DOUTB1_3 DOUTB1_4 DOUTB1_4 MEM_ED_16 DOUTB1_4 DOUTB1_5 DOUTB1_5 MEM_ED_17 DOUTB1_5 DOUTB1_6 DOUTB1_6 MEM_ED_18 DOUTB1_6 DOUTB1_7 DOUTB1_7 MEM_ED_19 DOUTB1_7 DOUTG1_2 DOUTG1_2 MEM_ED_20 DOUTG1_2 DOUTG1_3 DOUTG1_3 MEM_ED_21 DOUTG1_3 DOUTG1_4 DOUTG1_4 MEM_ED_22 DOUTG1_4 DOUTG1_5 DOUTG1_5 MEM_ED_23 DOUTG1_5 DOUTG1_6 DOUTG1_6 MEM_ED_24 DOUTG1_6 DOUTG1_7 DOUTG1_7 MEM_ED_25 DOUTG1_7 DOUTR1_2 DOUTR1_2 MEM...

Page 50: ...LK1 CCLK1 CCLK1 VIN1_6 BI1_7 MEM_ED_20 VIN1_7 GI1_2 MEM_ED_19 VIN1_4 BI1_5 MEM_ED_18 VIN1_5 BI1_6 MEM_ED_17 VINFID1 VINFID1 MEM_ED_16 VIN1_0 CONST0 MEM_XWR_3 VIN1_1 BI1_2 MEM_XWR_2 VIN1_2 BI1_3 DREQ_7 VIN1_3 BI1_4 XDACK_7 VINVSYNC1 VINVSYNC1 XDACK_6 VINHSYNC1 VINHSYNC1 DREQ_6 Pin multiplex mode 2 First MUX Function Second MUX Function Third MUX Function Fourth MUX Function CMPX_MODE_9 1 0 CMPX_MOD...

Page 51: ...DISP0N APIX0_SB_1 APIX0_SB_1 GPIO_PD_1 DISP1P DISP1P DISP1P GPIO_PD_2 GPIO_PD_2 DISP1N DISP1N DISP1N GPIO_PD_3 GPIO_PD_3 DISP2P DISP2P GPIO_PD_4 GPIO_PD_4 DISP2N DISP2N GPIO_PD_5 GPIO_PD_5 DISP3P DISP3P GPIO_PD_6 GPIO_PD_6 DISP3N DISP3N GPIO_PD_7 GPIO_PD_7 DISP4P APIX0_SB_2 APIX0_SB_2 GPIO_PD_8 DISP4N APIX0_SB_3 APIX0_SB_3 GPIO_PD_9 DISP5P DISP5P GPIO_PD_10 GPIO_PD_10 DISP5N DISP5N GPIO_PD_11 GPIO...

Page 52: ...1 GPIO_PD_0 ES2 CONST0 TSG_6 TSG_6 GPIO_PD_1 ES1 GPIO_PD_1 ES2 CONST0 TSG_7 TSG_7 GPIO_PD_2 APIX1_SB_0 TSG_8 TSG_8 GPIO_PD_3 APIX1_SB_1 TSG_9 TSG_9 GPIO_PD_4 APIX1_SB_2 TSG_10 TSG_10 GPIO_PD_5 APIX1_SB_3 TSG_11 TSG_11 GPIO_PD_6 APIX1_SB_4 TSG_12 TSG_12 GPIO_PD_7 APIX1_SB_5 Initial state for ES1 Initial state for ES2 Pin multiplex mode 6 First MUX Function Second MUX Function CMPX_MODE_6 0 0 1 Func...

Page 53: ... GPIO_PD_8 HOST_SPI_DI HOST_SPI_DI GPIO_PD_9 HOST_SPI_DO HOST_SPI_DO GPIO_PD_10 HOST_SPI_SS HOST_SPI_SS GPIO_PD_11 Initial state for ES1 Initial state for ES2 Pin multiplex mode 10 First MUX Function Second MUX Function Third MUX Function CMPX_MODE_10 1 0 CMPX_MODE_2 1 0 00 XX 01 0X 10 XX Functional Group UART1 2 SPI m 1 GPIO 19 16 SPI m 1 SD Pin Name 1st Function 2nd Function 3rd Function UART_SI...

Page 54: ...Second MUX Function CMPX_MODE_11 0 CMPX_MODE_2 1 0 0 XX 1 0X Functional Group SPI m 0 GPIO 23 20 Pin Name 1st Function 2nd Function SPI_DI0 SPI_DI0 GPIO_PD_20 SPI_DO0 SPI_DO0 GPIO_PD_21 SPI_SS0 SPI_SS0 GPIO_PD_22 SPI_SCK0 SPI_SCK0 GPIO_PD_23 Initial state for ES1 Initial state for ES2 ...

Page 55: ...Serial Data Output 1 positive L APIX SDIN1M A13 A I Serial Data Input 1 negative L APIX VCM1 A14 A Common Mode decoupling for input 1 L APIX SDIN1P B13 A I Serial Data Input 1 positive L APIX RREF D11 A Reference resistor for bias L APIX ATST C10 A Analog test port L APIX SDIN0M A9 A I Serial Data Input 0 negative L APIX VCM0 A8 A Common Mode decoupling for input 0 L APIX SDIN0P B9 A I Serial Data...

Page 56: ...DR2 DDRTYPE AF15 D I DDR2 MCKE_START AE22 D I DDR2 IDLLRST AD22 D I Test pin pull down to VSS through high resistance ST DDR2 MA_13 AE23 D O Memory Address H DDR2 MA_8 AF23 D O Memory Address H DDR2 MA_9 AD23 D O Memory Address H DDR2 MA_12 AF24 D O Memory Address H DDR2 MA_4 AE24 D O Memory Address H DDR2 ODTCONT AC22 D O On Die termination control L DDR2 MA_11 AE25 D O Memory Address H DDR2 MA_6...

Page 57: ...ff chip driver ref voltage DDR2 ODT N23 I A On die termination ref voltage DDR2 MDQ_19 M23 D IO Memory Data H DDR2 MDQ_18 M24 D IO Memory Data H DDR2 MDQ_21 M25 D IO Memory Data H DDR2 MDQ_20 L23 D IO Memory Data H DDR2 MDQSN_2 L26 D IO Memory Data Strobe HiZ DDR2 MDQSP_2 K26 D IO Memory Data Strobe HiZ DDR2 MDQ_17 L24 D IO Memory Data H DDR2 MDQ_16 L25 D IO Memory Data H DDR2 MDQ_22 L22 D IO Memo...

Page 58: ...ISP6P P1 D IO Display 0 output channel 6p Default DOUTG0_4 TTL mode HiZ MSIO DISP0 DISP6N P2 D IO Display 0 output channel 6n Default DOUTG0_5 TTL mode HiZ MSIO DISP0 DISP7P P3 D IO Display 0 output channel 7p Default DOUTG0_6 TTL mode HiZ MSIO DISP0 DISP7N P4 D IO Display 0 output channel 7n Default DOUTG0_7 TTL mode HiZ MSIO DISP0 DISP8P R1 D IO Display 0 output channel 8p Default DOUTB0_0 TTL m...

Page 59: ...O1 C2 D O Video output interface 1 dot clock output L STDIO DISP1 VSYNC1 D3 D IO Video output interface 1 vertical sync output vertical sync input in external sync mode 1 HiZ 2 L 3 HiZ STDIO DISP1 DE1 C1 D O DE CSYNC L STDIO DISP1 HSYNC1 D2 D IO Video output interface 1 horizontal sync output Horizontal sync input in external sync mode HiZ STDIO DISP1 DOUTB1_3 E3 D O Digital RGB output1 B3 1 L 2 H...

Page 60: ...clock HiZ POD I2C0 I2C_SDA0 AC20 D IO I2C Data HiZ POD I2C1 I2C_SCL1 AF20 D IO I2C clock HiZ POD I2C1 I2C_SDA1 AE20 D IO I2C Data HiZ POD I2S I2S_WS AC7 D IO Word Select HiZ PD I2S I2S_SDO AD7 D O Serial Data Output HiZ PD I2S I2S_SDI AC8 D I Serial Data Input STDIO I2S I2S_SCK AD8 D IO I2S Clock Output HiZ PD I2S I2S_ECLK AF8 D I I2S Clock Input optional HiZ PD ICE RTCK B7 D O Return test clock H...

Page 61: ...EA_11 B21 D O Address bus L STDIO MEMC MEM_EA_12 A21 D O Address bus L STDIO MEMC MEM_EA_13 D20 D O Address bus L STDIO MEMC MEM_EA_14 C20 D O Address bus L STDIO MEMC MEM_EA_15 B20 D O Address bus L STDIO MEMC MEM_EA_16 A20 D O Address bus L STDIO MEMC MEM_EA_17 D19 D O Address bus L STDIO MEMC MEM_EA_18 C19 D O Address bus L STDIO MEMC MEM_EA_19 B19 D O Address bus L STDIO MEMC MEM_EA_20 A19 D O...

Page 62: ...D I SPI1 Master Data Input MISO HiZ STDIO SPI m 1 SPI_DO1 AE19 D O SPI1 Master Data Output MOSI STDIO SPI m 1 SPI_SS1 AD19 D O SPI1 Master Slave Select L STDIO SPI m 1 SPI_SCK1 AC19 D O SPI1 Master serial clock L STDIO SPI s Host HOST_SPI_SCK AF11 D I HOST SPI Clock HiZ PU SPI s Host HOST_SPI_DI AE11 D I HOST SPI Data Input MOSI HiZ PU SPI s Host HOST_SPI_DO AD11 D O HOST SPI Data Output MISO L ST...

Page 63: ...N2 AD17 D I UART2 serial input HiZ PD UART2 UART_SOUT2 AC17 D O UART2 serial output H STDIO IO A Analog D Digital I Input O Output IO Bidirectional Input Output Initial state after reset H High L Low HiZ High Impedance 1 First hardware multiplex function 2 Second hardware multiplex function 3 Third hardware multiplex function Type PD Pull Down PU Pull Up ST Schmitt Trigger CLK Clock POD Pseudo Ope...

Page 64: ...tput 1 positive Keep the pin open SDIN1M Serial Data Input 1 negative Keep the pin open VCM1 Common Mode decoupling for input 1 Keep the pin open SDIN1P Serial Data Input 1 positive Keep the pin open RREF Reference resistor for bias Keep the pin open XTAL0 Crystal reference Keep the pin open XTAL1 Crystal reference Keep the pin open ATST Analog test port Keep the pin open SDIN0M Serial Data Input ...

Page 65: ...o VSS through high resistance IDLLRST Test pin Pull down to VSS through high resistance MA_13 Keep the pin open MA_8 Keep the pin open MA_9 Keep the pin open MA_12 Keep the pin open MA_4 Keep the pin open ODTCONT Keep the pin open MA_11 Keep the pin open MA_6 Keep the pin open MA_7 Keep the pin open MA_0 Keep the pin open MA_5 Keep the pin open MA_3 Keep the pin open MA_2 Keep the pin open MA_10 K...

Page 66: ...l down to VSS through high resistance MDQ_23 Pull down to VSS through high resistance VREF1 Connect to DDRVDE 2 V Reference voltage MDQ_27 Pull down to VSS through high resistance MDQ_26 Pull down to VSS through high resistance MDQ_29 Pull down to VSS through high resistance MDQ_25 Pull down to VSS through high resistance MDQSN_3 Pull down to VSS through high resistance MDQSP_3 Pull down to VSS th...

Page 67: ...mode Pull up to VDDE or pull down to VSS through high resistance DISP9P Display 0 output channel 9p Default DOUTB0_2 TTL mode Pull up to VDDE or pull down to VSS through high resistance DISP9N Display 0 output channel 9n Default DOUTB0_3 TTL mode Pull up to VDDE or pull down to VSS through high resistance DISP10P Display 0 output channel 10p Default DOUTB0_4 TTL mode Pull up to VDDE or pull down t...

Page 68: ...ync mode Pull up to VDDE or pull down to VSS through high resistance VSYNC1 Video output interface 1 vertical sync output vertical sync input in external sync mode Pull up to VDDE or pull down to VSS through high resistance DOUTB1_2 Digital RGB output1 B2 Pull up to VDDE or pull down to VSS through high resistance DOUTB1_3 Digital RGB output1 B3 Pull up to VDDE or pull down to VSS through high res...

Page 69: ...t optional Pull up to VDDE or pull down to VSS through high resistance I2S_SCK I2S Clock Output Keep the pin open I2S_SDI Serial Data Input Pull up to VDDE or pull down to VSS through high resistance INT_A_3 Keep the pin open INT_A_2 Keep the pin open INT_A_1 Keep the pin open INT_A_0 Keep the pin open TDO Keep the pin open TRACECLK Pull up to VDDE or pull down to VSS through high resistance TDI K...

Page 70: ... resistance MEM_ED_7 Pull up to VDDE or pull down to VSS through high resistance MEM_ED_8 Pull up to VDDE or pull down to VSS through high resistance MEM_ED_9 Pull up to VDDE or pull down to VSS through high resistance MEM_ED_10 Pull up to VDDE or pull down to VSS through high resistance MEM_ED_11 Pull up to VDDE or pull down to VSS through high resistance MEM_ED_12 Pull up to VDDE or pull down to...

Page 71: ...h resistance MEM_EA_19 Pull up to VDDE or pull down to VSS through high resistance MEM_EA_20 Pull up to VDDE or pull down to VSS through high resistance MEM_EA_21 Pull up to VDDE or pull down to VSS through high resistance MEM_EA_22 Pull up to VDDE or pull down to VSS through high resistance MEM_EA_23 Pull up to VDDE or pull down to VSS through high resistance MEM_EA_24 Pull up to VDDE or pull dow...

Page 72: ...Supply seperated ground plane recommented connection via filter to digital ground n a PWM_O3 PWM Output Keep the pin open PWM_O2 PWM Output Keep the pin open PWM_O1 PWM Output Keep the pin open PWM_O0 PWM Output Keep the pin open SPI_DI0 SPI0 Master Data Input MISO Pull up to VDDE or pull down to VSS through high resistance SPI_DO0 SPI0 Master Data Output MOSI Pull up to VDDE or pull down to VSS t...

Page 73: ...gh high resistance OSC_FILTER characteristic of post oscillator filter Connect to VDDE 3 3V via a high resistance OSC_MODE1 oscillator mode 1 Connect to VSS OSC_BIAS0 Oscillator bias level 0 Connect to VSS OSC_BIAS1 Oscillator bias level 1 Connect to VSS OSC_MODE0 oscillator mode 0 Connect to VSS XRST System Reset n a PLLTDTRST PLL Transition Delay Test Reset Keep the pin open XTRST Test reset n a...

Page 74: ...MB88F332 Indigo Graphics Display Controller The MB86R02 Jade D would operate as the master in the system and would control the MB88F332 Indigo via its APIX interface MB86R02 Jade D would be responsible for the generation of all graphics and would provide display control in this example one dashboard display and one head up display Using its embedded TCON the MB86R02 Jade D could drive one of the d...

Page 75: ...ory Map This chapter shows the memory map and the register map of the MB86R02 Jade D device 3 1 Memory Map of LSI Figure 3 1 shows the memory map of MB86R02 Jade D The device is booted from 0000_0000H in ROM as shown on the left side of Figure 3 1 ...

Page 76: ...3 2 MB86R02 Jade D Hardware Manual V1 64 Figure 3 1 Memory map 1 ...

Page 77: ...3 3 MB86R02 Jade D Hardware Manual V1 64 Figure 3 2 Memory map 2 ...

Page 78: ... endian addressing 1 DMACA DMACB DMACSA DMACDA Word 32 bit Half word 16 bit Byte 8 bit For byte and half word access use little endian addressing 1 UART RFR TFR DLL DLM Word 32 bit Byte 8 bit For byte access use little endian addressing 1 GPIO PDR0 PDR1 PDR2 Word 32 bit Byte 8 bit For byte access use little endian addressing 1 Others All registers other than the above Word 32 bit 1 Little endian a...

Page 79: ...g Harvard architecture 16KB instruction cache 16KB data cache 16KB instruction TCM ITCM 16KB data TCM DTCM JAVA acceleration Jazelle technology Coprocessor interface MMU Memory Management Unit Embedded ETM9CS Single for real time tracing Supports both big and little endian 4 3 Block diagram of ARM926EJ S core The block diagram of the ARM926EJ S core is shown in Figure 4 1 ARM926EJ S Core Block 16k...

Page 80: ...erence documents are listed below for this purpose ARM926EJ S ARM926EJ S Product Overview ARM926EJ S r0p4 r0p5 Technical Reference Manual DDI0198D ARM9EJ S Revision r1p2 Technical Reference Manual m DDI0222B ARM926EJ S Product Overview DVI0035B The URL of the material published is as follows http www arm com documentation ARMProcessor_Cores index html ETM9CS Single relation CoreSight ETM9 r0p0 Tec...

Page 81: ...be used Main PLL control PLL oscillation control including stop PLL oscillation stabilization wait time control SSCG control refer to the SSCG chapter for details and a description of the registers Clock gear control The clock frequency of the ARM core and the AXI AHB and APB busses can be changed separately Control of the clock Supply Stop to the ARM core AXI AHB and APB modules Reset Generator G...

Page 82: ...ARMBCLK ARM B clock used for ARM ETM module MLB 0 166 yes SELCCLK 1 yes PACLK x APB clock used for all APB peripherals 0 41 625 yes SELCCLK 1 yes HBCLK AHB B clock used for GDC AXI DDR2 IF MLB internal 0 166 yes SELCCLK 1 yes HACLK y AHB A clock used for MLB SD I2S module 0 83 3 yes SELCCLK 1 yes HACLK x AHB A clock used for the remaining AHB modules 0 83 3 yes SELCCLK 1 yes HACLKCRG AHB A clock u...

Page 83: ...et CLKX External clock from pin CLK Oscillator Clock domains XTAL0 XTAL1 APIX Ashell CLKY SSCG PLLCLK PLLCLKM CFG CFG from RH Register IF CCLK_O DISP DPERI CLKDIV CLKGATE CFG Figure 5 1 CRG location in the device 5 5 Operation This section describes the operation of the CRG unit 5 5 1 Reset Generation Factors The following reset sources exist 1 External reset XRST pin input The entire chip is init...

Page 84: ...set is asserted This software reset generates the internal signal which does not reset as CRSTn 3 XSRST reset request from a debugging tool This signal is a reset request from a debugging tool e g MultiICE and an internal reset request can be transmitted by the tool through the XSRST pin This module recognizes the reset signal as the same reset request as that of an external reset 4 XTRST built in...

Page 85: ...ode DBGACK 1 during PLL oscillation stabilization waiting time CRG clears the watchdog timer In addition it monitors the standby mode of the ARM9 core and clears the watchdog timer automatically in standby mode standby mode 1 Reset output signal The reset signal output by the reset generator is as follows depending on the reset source HRESETn AHB APB bus reset This internal reset signal initialize...

Page 86: ...urces and reset output signals Reset output Reset source External reset Software reset Input XSRST XTRST Watchdog reset HRESETn Asserted Asserted Asserted Not asserted Asserted Output XSRST Asserted Asserted Not asserted Not asserted Asserted Internal XTRST Asserted Not asserted Not asserted Asserted Not asserted CRSTn Asserted Not asserted Asserted Not asserted Asserted ...

Page 87: ... CRHA CRHB CRPA CRPB CRAM Please be aware that each clock is enabled after a reset For power saving reasons clocks for non active modules should be disabled CRG REF OSC CDR APIX PLL 500MHz 250MHz configuration Feedback divider N Main PLL up to 666 MHz SSCG 400 7 00MH z configuration Bypass enable Rate etc DIV 1 2 CCLK Not Modulated System clock XTAL0 XTAL1 m u x External pin SELXCK 0 1 PLLBYPASS C...

Page 88: ...ate CCLK ARMA_O Used for ARM DDR IF DIV 1 LX Gate STOP ARMAGATE 0 ARMADM 2 0 ARMB_O ETMclock STOP ARMBGATE 0 ARMBDM 2 0 Figure 5 4 Clock Structure ARM clocks For each divider Lx is 1 2 4 8 16 PLLCLKM CCLK_O Used for DCLK Figure 5 5 Clock structure DCLK ...

Page 89: ... 1 LX Gate PACLKX_O IRC UART CCLK Gate STOP PAGATE X PADM 2 0 PACLKcrg_O CRG STOP Gate HBCLKMLB_O MLB DIV 1 LX Gate HACLKY_O MLB I2S SD DIV 1 LX HBDM 2 0 HADM 2 0 STOP HBGATE X STOP HAGATE X Figure 5 6 Clock structure non modulated clocks part 1 ...

Page 90: ...B86R02 Jade D Hardware Manual V1 64 DIV 1 L Gate CCLK HACLKX_O Gate DIV 1 L Gate STOP HAGATE X HADM 2 0 HACLKcrg_O HBCLKX_O STOP STOP HBGATE X HBDM 2 0 Figure 5 7 Clock Structure non modulated AHB CLK part 2 ...

Page 91: ...bilization waiting state as shown below the time based timer is cleared 1 External reset is asserted M and m of LUWMODE in the 5 1 2 PLL control register CRPR PLL oscillation stabilization waiting ERSTn PLL reset CLK 1 M PLL clock CCLK HRESETn PLLREADY PLLBYPASS 6 CLK cycles a External reset deasserted XRST b ERSTn reset CRG internal signal c PLL reset deasserted d PLL ready e HRESETn deasserted a...

Page 92: ...g reset is asserted Frequency change The oscillation frequency and frequency dividing ratio M of PLL fCLK N are set by PLLMODE 4 0 bit of the PLL control register CRPR and the frequency can be changed during operation see Table 5 3 Do not change PLLMODE 4 0 when the PLLBYPASS bit of the PLL control register CRPR is 0 The initial value at start up is determined by the external pin PLLBYPASS and CRI...

Page 93: ...5 265 63 265 63 132 81 66 41 132 81 33 20 0 0 0 0 0 64 3 25 00 533 33 266 67 266 67 133 33 66 67 133 33 33 33 0 0 1 0 1 51 2 20 8333 531 25 265 62 265 62 132 81 66 41 132 81 33 20 0 0 0 0 1 80 3 20 00 533 33 266 67 266 67 133 33 66 67 133 33 33 33 1 1 1 1 1 PLLSTOP PLLBYPASS The main clock CCLK of the CRG module can be dynamically switched between the PLL clock and an external input clock CLK usin...

Page 94: ...ower management interrupt mode waiting This CRG module does not have a function to stop the ARMCLK signal in standby mode ARMCLK Clock Reset Generator ARM926EJ S CLK clock gate STANDBYWFI Internal clock Figure 5 12 STANDBYWFI mode ARM926EJ S 2 STOP mode When the STANDBYWFI ARM926EJ S signal is set to 1 when STOPEN 1 the state changes to STOP mode through the standby mode if STOPEN 1 this module s ...

Page 95: ...abilization waiting state is skipped if PLLMODE 4 0 is 5 b11111 CLK STOP mode STOPEN STANDBYWFI PACLK0_STP STOP WAKEUP CCLK ARMA B CLK HACLK PACLK PLLBYPASS PLLRDY PLL clock PLL reset PLL oscillation stabilization waiting STOP CLK clock is able to stop while the value is 1 Figure 5 13 Stop mode ...

Page 96: ...gate of APB A bus 20H APB B bus clock gate control register CRPB To control clock gate of APB B bus 24H AHB B bus clock gate control register CRHB To control clock gate of AHB B bus 28H ARM core clock gate control register CRAM To control clock gate of ARM core 2CH DPERI0 2 clock gate control register CRDP0 TO control clock gate of DPERI0 30H DPERI1 3 clock gate control register CRDP1 TO control c...

Page 97: ... 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name R W Initial value Meaning of item and sign Address Address base address offset address of the register Bit Bit number of the register Name Bit field name of the register R W Attribution of read write of each bit field R0 Read value is always 0 R1 Read value is always 1 W0 Write value is always 0 and write access of 1 is ignored W1 Write value is always 1 and w...

Page 98: ...direct control enable 0 Disabled initial value Register PLLMODE is effective 1 Enabled Register PLLMODE has no effect Register PLLPDIV and PLLNDIV are active Note Do not change PLLDEN bit during PLLBYPASS bit is 0 30 24 PLLNDIV 6 0 PLL feedback divider value Has only effect if PLLDEN 1b PLLNDIV 6 0 NDIV allowed range 6 decimal 96 decimal Only values for which 250MHz fCCLK 333MHz is valid are allow...

Page 99: ...d PLLMODE 4 0 at the same time since clock switch of both external pin CLK and PLL clocks needs to be changed If they are changed at the same time CRG detects PLL oscillation frequency change and state becomes PLL oscillation stabilization waiting before PLL bypass mode Reference The initial value of this bit is settable with setting external pin PLLBYPASS 6 5 LUWMODE 1 0 PLL locked waiting mode T...

Page 100: ...M 1 CRIPM 0 00000 fCCLK fCLK 10 67 64 x 1 3 1 2 00001 fCCLK fCLK 13 33 80 x 1 3 1 2 00010 fCCLK fCLK 16 00 32 1 2 00011 fCCLK fCLK 16 50 33 1 2 00100 fCCLK fCLK 10 17 61 x 1 3 1 2 00101 fCCLK fCLK 12 75 51 x 1 2 1 2 00110 fCCLK fCLK 15 33 92 x 1 3 1 2 00111 reserved 01000 fCCLK fCLK 8 5 17 1 2 01001 reserved 01010 reserved 01011 reserved 11111 PLL stops Others Reserved setting prohibited fCCLK Clo...

Page 101: ...read value of these bits is always 0 7 ERST Internal reset of ERSTn monitoring This bit monitors internal signal of ERSTn 0 ERSTn is asserted 1 ERSTn is cancelled initial value The initial value of this bit is set to 1 by falling edge of ERSTn and writing 1 is ignored This bit is set by ERSTn 6 Reserved Reserved bits Write access is ignored and read value of these bits is always 0 5 Reserved Reser...

Page 102: ...1 First time The watchdog timer starts Second time or later The watchdog timer is cleared Writing 0 is ignored 1 0 WDTMODE 1 0 These bits set timing to clear watchdog timer Watchdog reset occurs at following period when 1 is written to WDTSET WDTCLR bits at the end 00 TCLK 2 n0 TCLK 2 n0 1 initial value 01 TCLK 2 n1 TCLK 2 n1 1 10 TCLK 2 n2 TCLK 2 n2 1 11 TCLK 2 n3 TCLK 2 n3 1 TCLK Cycle time of e...

Page 103: ... clock operation in the standby mode does not stop initial value 1 All bus clock operations in the standby mode are stopped Note clocks are not stopped immediately Note When changing state to stop mode write 1 to PLLBYPASS bit of CRPR 6 5 Reserved Reserved bits Write access is ignored and read value of these bits is always 0 4 Reserved Reserved bit Always write 0 to write access 3 SRST nSRST monit...

Page 104: ...s pulse width of software reset 0 TCLK 2 n0 3 TCCLK 7 initial value 1 TCLK 2 n1 3 TCCLK 7 TCLK Cycle time of reference clock CLK TCCLK Cycle time of internal signal CCLK n0 7 n1 12 Pulse width of software reset depends on the CLK cycle time and internal operation frequency setting Select the bit that is corresponded to the system ...

Page 105: ... ignored and read value of these bits is undefined 15 Reserved Reserved bit Write access is ignored and read value of these bits is always 0 14 12 ARMBDM 2 0 ARMBCLK frequency dividing mode These bits set frequency dividing ratio of ARMBCLK 000 fARMBCLK fCCLK 1 1 001 fARMBCLK fCCLK 1 2 initial value 010 fARMBCLK fCCLK 1 4 011 fARMBCLK fCCLK 1 8 100 fARMBCLK fCCLK 1 16 Others Reserved setting prohi...

Page 106: ...d setting prohibited fPACLK Clock frequency of PACLK fCCLK Clock frequency of CCLK 2 0 HADM 2 0 HACLK frequency dividing mode These bits set frequency dividing ratio of HACLK 000 fHACLK fCCLK 1 1 001 fHACLK fCCLK 1 2 010 fHACLK fCCLK 1 4 initial value 011 fHACLK fCCLK 1 8 100 fHACLK fCCLK 1 16 Others Reserved setting prohibited fHACLK Clock frequency of HACLK fCCLK Clock frequency of CCLK Note ARM...

Page 107: ...0 R0 R W R W R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Bit field Description No Name 31 16 Unused bits Write access is ignored and read value of these bits is undefined 15 3 Reserved Reserved bits Write access is ignored and read value of these bits is always 0 2 0 HBDM 2 0 HBCLK frequency dividing mode These bits set frequency dividing ratio of HBCLK HBDM 2 0 Frequency dividing ratio of H...

Page 108: ... 1 1 1 1 1 1 1 1 1 1 1 Bit field Description No Name 31 24 Unused bits Write access is ignored and read value of these bits is undefined 23 0 HAGATE 23 0 HACLK clock gate control These bits control HACLK clock gate HAGATE n Description 0 HACLKn stops 1 HACLKn does not stop initial value HACLK0 AHB1 AHB2 APBBRG0 APBBRG1 APBBRG2 AHB2AHB HACLK1 External bus I F CCPB HACLK2 SRAM HACLK3 HDMAC HACLK4 Re...

Page 109: ... R W R W R W R W R W R W R W Initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit field Description No Name 31 16 Unused bits Write access is ignored and read value of these bits is undefined 15 0 PAGATE 15 0 PACLK clock gate control These bits control PACLK clock gate PAGATE n Description 0 PACLKn stops 1 PACLKn does not stop initial value PACLK0 IRC PACLK1 EXIRC PACLK2 UART0 UART1 PACLK3 GPIO PACLK...

Page 110: ... R W R W R W R W R W R W R W R W R W R W R W R W Initial value X X X X X X X X X X X X X X X X Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Reserved R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit field Description No Name 31 16 Unused bits Write access is ignored and read value of these bits is undefined 15 0 Reserved 15 0 Re...

Page 111: ...R W Initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit field Description No Name 31 16 Unused bits Write access is ignored and read value of these bits is undefined 15 0 HBGATE 15 0 HBCLK clock gate control These bits control HBCLK clock gate HBGATE n Description 0 HBCLKn stops 1 HBCLKn does not stop initial value HBCLK0 GDC HOST IF HBCLK1 GDC DRAW GEO MBUS2AXI DRW HBCLK2 Reserved HBCLK3 GDC DISP0 ...

Page 112: ... 0 4 ARMBGATE ARMBCLK clock gate control These bits control ARMBCLK clock gate 0 ARMBCLK stops 1 ARMBCLK does not stop initial value This clock is used to ATCLK of ETM9CS Single 3 1 Reserved Reserved bits Write access is ignored and read value of these bits is always 1 0 ARMAGATE ARMACLK clock gate control These bits control ARMACLK clock gate 0 ARMACLK stops 1 ARMACLK does not stop initial value ...

Page 113: ...ES RES R W R1 R1 R1 R1 R1 R1 R1 R1 R1 R1 R1 R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit field Description No Name 31 16 Unused bits The write access is ignored and read value of these bits is undefined 15 5 Reserved Reserved bits Write access is ignored and read value of these bits is always 1 4 Reserved Reserved bits Write access is ignored and read value of these bits i...

Page 114: ...t Frequency Range switchable 400MHz 700MHz Modulation Period variable from 1 1 048 320 to 1 256 of PLL clock Modulation Period Delta continuously from 0 to 12 5 of the modulation period Modulation type non modulated downspread center spread default Modulation peak Default 1 0 Center spread 1 56 to 1 56 Downspread 0 to 1 56 Upspread 0 to 1 56 not used Modulation shape triangle dual triangle Frequen...

Page 115: ... interrupt Enable interrupt SSCG runs Figure 6 2 SSCG setting sequence of the frequency offset and SSCG mode Note When SSCG_PEAK_FREQUENCY is set to 1 the modulation peak value will be doubled In order to maintain the same modulation peak the values of SSCG_FSTEP and SSCG_FOFFSET must therefore be divided by 2 Note Please note that an important Application Note exists concerning EMI optimization a...

Page 116: ...ems and sign Register address Register address shows the address Offset address of the register Bit number Bit number shows bit position of the register Field name Field name shows bit name of the register R W R W shows the read write attribute of each bit field R Read W Write W1C Writing a value of 1 clears the register Reset value Reset value indicates the value of each bit field immediately aft...

Page 117: ...measurement duration Base address 30H SSCG_COUNT_TYPE Measurement type Base address 34H SSCG_COUNT_TRIG Trigger to start a measurement Base address 44H SSCG_CNTOUTFREQ Measurement result Build average if SSCG_CNT_AVERAGE 1 Base address 48H SSCG_RESET_CTRL Software Reset Register Description SSCG_PERIOD Register address BaseAddress 0H Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14...

Page 118: ...t of modulated frequency 0x0A3D 70A3 0 5 offset of modulated frequency 0xF5C2 8F5D 0 5 offset of modulated frequency 0xEB85 1EB9 1 offset of modulated frequency SSCG_IEN Register address BaseAddress 14H Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field name IEn_Frequency_Limit R W RW Reset value 0H Interrupt Enable Register Bit 0 IEn_Frequency_L...

Page 119: ... 1 Enable SSCG spread spectrum unit if enabled you are NOT allowed to modify any configuration registers except SSCG_ENABLE and SSCG_FREQUENCY_MEASUREMENT SSCG_FREQUENCY_MEASUREMENT Register address BaseAddress 2CH Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field name SSCG_CNTLEN SSCG_CNTSTART R W RW RW Reset value 25H 0H Measurement position a...

Page 120: ...address BaseAddress 44H Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field name SSCG_OUTFREQ R W R Reset value 0H Measurement result Build average if SSCG_CNT_AVERAGE 1 Bit 24 0 SSCG_OUTFREQ Used for debugging Measured output clock count SSCG_RESET_CTRL Register address BaseAddress 48H Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15...

Page 121: ...fault SSCG_PEAK_FREQUENCY 0 default SSCG_PERIOD_JITTER 10 default SSCG_TYPE SSCG_PERIOD PERIOD_DELTA Modulation Peak SSCG_STEP 3 Center Spread 0xAC 0x8A 0 5 0x6ED0 1 0 0xDDA0 1 5 0x1 4C70 2 0 0x1 BB40 2 5 0x2 2A10 3 0 0x2 9820 2 Upspread 0xAC 0x8A 0 5 0x3768 1 0 0x6ED0 1 5 0xA638 2 0 0xDDA0 2 5 0x1 1508 3 0 0x1 4C70 1 Downspread 0xAC 0x8A 0 5 0x3768 1 0 0x6ED0 1 5 0xA638 2 0 0xDDA0 2 5 0x1 1508 3 ...

Page 122: ...lt PERIOD_DELTA 10 SSCG_PEAK_FREQUENCY 0 SSCG_TYPE SSCG_PERIOD PERIOD_DELTA Modulation Peak SSCG_STEP 3 Centre Spread 0x7B 0x70 0 5 0x9913 1 0 0x1 3226 1 5 0x1 CB39 2 Upspread 0x7B 0x70 0 5 0x4C89 1 0 0x9913 1 5 0xE59B 1 Downspread 0x7B 0x70 0 5 0x4C89 1 0 0x9913 1 5 0xE59B Table 6 4 SSCG speed of 20KHz refer to 666MHz PLL clock ...

Page 123: ...275 1 0 0x1 04EB 1 5 0x1 875F 2 0 0x209D6 2 5 0x2 8C49 3 0 0x3 0EC1 Table 6 5 SSCG speed of 35KHz refer to 666MHz PLL clock 6 4 1 4 Parameter setting for SSCG speed of 50KHz Given SSCG_ FREQUENCY_OFFSET 0 default SSCG_PEAK 0 default SSCG_PERIOD_JITTER 10 default SSCG_TYPE SSCG_PERIOD SSCG_PERIOD_JITTER Modulation Peak SSCG_STEP 3 Center spread 0x33 0x29 0 5 0x1 75A8 1 0 0x2 EB50 1 5 0x460F8 2 0 0x...

Page 124: ...wn below Sscg_period 35KHz Sscg_period_period 10 Centre spread Sscg degree 1 5 No frequency offset disable interrupt Default setting Desired Indiviual setting Start SSCG by setting SSCG_ENABLE 1 Change Configuration SSCG_ENABLE 0 reset SSCG runs NO YES NO YES Refer to Table 1 Table5 Table6 Table7 666MHz PLL clock Figure 6 7 SSCG programming flow ...

Page 125: ...nality and operation of the Chip Control Module CCNT 7 1 Overview The Chip Control Module referred to from here on as CCNT is an INT signal interrupt conversion process pulse level from each module and it controls soft resets the AXI priority level and AXI BUS Waits MBUS2AXI Bridge exclusive use ...

Page 126: ...pin interface o Displays the signal level of the external pin in status The MediaLB interface Switches the method of MediaLB of the AHB read data output 7 3 Supply clock The APB clock signal is supplied to the CCNT module Please refer to chpater 5 Clock Reset Generator for information about setting the frequency and the control specifications of the APB clock ...

Page 127: ...rupt status mask register FFF42020 CGPIO_IP GPIO interrupt polarity setting register FFF42024 CGPIO_IM GPIO interrupt mode setting register FFF42028 CAXI_BW AXI bus wait cycle set register FFF4202C CAXI_PS AXI priority setting register FFF42030 CMUX_MD Multiplex mode setting register FFF42034 CEX_PIN_ST External pin status register FFF42038 CMLB MediaLB set register FFF4203C Reserved Access prohib...

Page 128: ...ems and sign Address Address shows the address Base address Offset address of the register Bit Bit shows bit number of the register Name Name shows bit field name of the register R W R W shows the read write attribute of each bit field R0 The read value is always 0 R1 The read value is always 1 W0 The write value is always 0 If 1 is written it is ignored W1 The write value is always 1 If 0 is writ...

Page 129: ... 1 0 Name CHIPNAME 7 0 VERSION 7 0 R W R R R R R R R R R R R R R R R R Initial value 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 Bit field Function Number Name 31 16 YEAR 15 0 Development year of the GDC as four digits For this GDC it reads 2010 h 15 8 CHIPNAME 7 0 LSI identification name is shown by the identification number For this GDC it reads 11 h 7 0 VERSION 7 0 The version of the GDC is shown The GDC r...

Page 130: ...ial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit field Function Number Name 31 1 Reserved Reserved Writes are ignored Reads will return a 0 at all times 0 SFTRST Soft Reset Reset this unit by writing 1 to this bit The various units GDC DDR2 CAN SDMC MediaLB I2S SPI I2C PWM UART GPIO and HDMAC are reset The value of this bit should be set to 0 again at reset release 0 No Reset initial value 1 Reset Ja...

Page 131: ...served Reserved Writes are ignored Reads will return a 0 at all times 28 INT28 HBUS2AXI This bit is set to 1 if i_int28 becomes 1 Clearing is done by writing a 0 to this bit If Bit28 of the INT Mask register is set to mask 0 this bit is fixed at 0 0 There is no interrupt initial value 1 There is an interruption 27 INT27 MBUS2AXI Draw This bit is set to 1 if i_int27 becomes 1 Clearing is done by wr...

Page 132: ... 0 this bit is fixed at 0 0 There is no interrupt initial value 1 There is an interruption 23 6 Reserved Reserved Writes are ignored Reads will return a 0 at all times 5 INT5 MBUS2AXI Cap This bit is set to 1 if i_int5 becomes 1 Clearing is done by writing a 0 to this bit If Bit5 of the INT Mask register is set to mask 0 this bit is fixed at 0 0 There is no interrupt initial value 1 There is an in...

Page 133: ...errupt for MediaLB INT information becomes valid by writing 1 to this bit 0 Mask initial value 1 INT31 valid 30 29 Reserved Reserved Writes are ignored Reads will return a 0 at all times 28 INT28 Mask Interrupt for HBUS2AXI INT information becomes valid by writing 1 to this bit 0 Mask initial value 1 INT28 valid 27 INT27 Mask Interrupt for MBUS2AXI Draw INT information becomes valid by writing 1 t...

Page 134: ... ignored Reads will return a 0 at all times 3 INT3 Mask ADC3 interrupt mask INT information becomes valid by writing 1 to this bit 0 Mask initial value 1 INT3 valid 2 INT2 Mask ADC2 interrupt mask INT information becomes valid by writing 1 to this bit 0 Mask initial value 1 INT2 valid 1 INT1 Mask ADC1 interrupt mask INT information becomes valid by writing 1 to this bit 0 Mask initial value 1 INT1...

Page 135: ...s 23 0 GPIO_INT_status GPIO interrupt status Clear by writing 0 Indicates a GPIO interrupt 0 No interrupt occurred 1 Interrupt occurred 7 4 7 GPIO interrupt status mask register CGPIO_ISTM This register controls GPIO related interrupts It is used to mask the interrupt status of each GPIO interrupt The register takes effect regardless of the input output situation at the time it is set Each bit tha...

Page 136: ...ds will return a 0 at all times 23 0 GPIO_INT_enable GPIO interrupt enable Set whether the interrupt of each bit occurs according to the value which the external pins GPIO23 0 sample with the internal clock 0 Interrupt doesn t occur 1 Occur interrupt based on the following register setting ...

Page 137: ...red Reads will return a 0 at all times 23 0 GPIO_INT_polarity GPIO interrupt polarity An interrupt occurs according to the following values 0 Detect on level 0 or negative edge depends on GPIO_INT_mode 1 Detect on level 1 or positive edge depends on GPIO_INT_mode 7 4 9 GPIO interrupt mode setting register CGPIO_IM This register controls the level edge mode detection type for GPIO interrupts The re...

Page 138: ...anual V1 64 Writes are ignored Reads will return a 0 at all times 23 0 GPIO_INT_mode GPIO_INT_mode GPIO interrupt mode 0 Level sensitive 0 or 1 depends on GPIO_INT_polarity 1 Edging sensitive Pos or neg is shown in GPIO_INT_polarity ...

Page 139: ... BUS of MBUS2AXI Bridge between the transactions can be set by this bit This setting can set even 0H No Wait FH 15Cycle Wait The initial value is 0H No Wait Note 1Cycle is AXI 1Clock 23 20 Draw_RWAIT Read Wait The Wait time of AXI Write BUS of MBUS2AXI Bridge between the transactions can be set by this bit This setting can set even 0H No Wait FH 15Cycle Wait The initial value is 0H No Wait Note 1C...

Page 140: ... the transactions can be set by this bit This setting can set even 0H No Wait FH 15Cycle Wait The initial value is 0H No Wait Note 1Cycle is AXI 1Clock 3 0 PrimaryAHB_WWAI T Read Wait The Wait time of AXI Read BUS of AHB2AXI Bridge between the transactions can be set by this bit This setting can set even 0H No Wait FH 15Cycle Wait The initial value is 0H No Wait Note 1Cycle is AXI 1Clock ...

Page 141: ... R W R W R W R R W R W R W R R W R W R W R R W R W R W Initial value 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 Bit field Function Number Name 31 19 Reserved Reserved Writes are ignored Reads will return a 0 at all times 18 16 P_SEL4 Priority Select4 The priority level of AXI interconnect bus can be set by this bitfield 000 0 001 1 010 2 011 3 100 4 initial value 15 Reserved Reserved Writes are ignored Reads...

Page 142: ...riority Select1 The priority level of AXI interconnect bus can be set by this bit 000 DispCap 001 AHB initial value 010 CPU 011 HBUS 100 DRAW 3 Reserved Reserved Writes are ignored Reads will return a 0 at all times 2 0 P_SEL0 Priority Select0 The priority level of AXI interconnect bus can be set by this bit 000 DispCap initial value 001 AHB 010 CPU 011 HBUS 100 DRAW ...

Page 143: ... table 11 see Overview chapter Selects SPI master interface 0 or GPIO 23 20 0 SPI master IF 0 is available at external Pins 1 GPIO 23 20 is available at eternal Pins CMPX_MODE2 1 must be 0 initial value 27 26 CMPX_MODE_10 Selects the first second or third pin multiplex function of pin multiplex table 10 see Overview chapter Selects UART 1 UART2 SPI master interface 1 or GPIO 19 16 SPI master inter...

Page 144: ...o inputs are available 19 18 CMPX_MODE_3 Selects the first or second pin multiplex function of pin multiplex table 5 see Overview chapter 00 TSG 12 4 Timing Signals are available 01 GPIO7 0 and DCLKIN0 available initial value 10 APIX1_SB GPIO1 0 and DCLKIN0 available 11 Sets default mode 17 16 CMPX_MODE_2 Selects the first or second pin multiplex function of pin multiplex table 2 see Overview chap...

Page 145: ... 11 8 CRIPM Display the status of PLL multiply number setting pin 7 4 Reserved Reserved Writes are ignored Reads will return a 0 at all times 4 CLK_SEL CLKSEL 0 Selects internal oscillator clock 1 Selects clock input from ECLK external 3 MPX_MODE_5 1 MPX_MODE_5 1 0 UART0 available 1 Memory Controller NAND Flash support available 2 MPX_MODE_5 0 Display the status of a set pin for external pin multi...

Page 146: ... 0 SEL_SPREAD Switch the method of MediaLB of the AHB read data output 0 CaseA see below 1 CaseB see below Switch the method of MediaLB of the AHB read data output case A Output word data HRDATA 31 24 23 16 15 8 7 0 BigEndian Word 0h Byte0 Byte1 Byte2 Byte3 Half Word 0h Byte0 Byte1 Byte2 Byte3 Half Word 2h Byte0 Byte1 Byte2 Byte3 Byte 0h Byte0 Byte1 Byte2 Byte3 Byte 1h Byte0 Byte1 Byte2 Byte3 Byte...

Page 147: ...2h Byte2 Byte3 Byte2 Byte3 Byte 0h Byte0 Byte0 Byte0 Byte0 Byte 1h Byte1 Byte1 Byte1 Byte1 Byte 2h Byte2 Byte2 Byte2 Byte2 Byte 3h Byte3 Byte3 Byte3 Byte3 LittleEndian Word 0h Byte3 Byte2 Byte1 Byte0 Half Word 0h Byte1 Byte0 Byte1 Byte0 Half Word 2h Byte3 Byte2 Byte3 Byte2 Byte 0h Byte0 Byte0 Byte0 Byte0 Byte 1h Byte1 Byte1 Byte1 Byte1 Byte 2h Byte2 Byte2 Byte2 Byte2 Byte 3h Byte3 Byte3 Byte3 Byte...

Page 148: ...0 0 0 0 Bit field Function Number Name 31 5 Reserved Reserved Writes are ignored Reads will return a 0 at all times 4 DRAW_MBUS_WTWAIT Transaction wait setting for write transaction The next transaction is not begun until the transaction is completed on an internal bus 0 Don t wait 1 Wait 3 DRAW_MBUS_RTWAIT Transaction wait setting for read transaction The next transaction is not begun until the t...

Page 149: ...ved Reserved Writes are ignored Reads will return a 0 at all times 30 28 Reserved 27 Reserved Reserved Writes are ignored Reads will return a 0 at all times 26 24 Reserved 23 Reserved Reserved Writes are ignored Reads will return a 0 at all times 22 20 SD_Endian The Endian switch of SD is controlled Bit 22 wSEL Endian switch 0 Little 1 Big Bit 21 HWSAP Hword byte swap switch signal at Big Bit 20 W...

Page 150: ...erved Writes are ignored Reads will return a 0 at all times 10 8 Reserved 7 Reserved Reserved Writes are ignored Reads will return a 0 at all times 6 4 Reserved 3 2 Reserved Reserved Writes are ignored Reads will return a 0 at all times 1 VideoCap_performa nce Do video capture performance improvement EC valid 0 Before measures of EC initial value 1 After measures of EC 0 AHB2AXI_BIGMOD E Toggle co...

Page 151: ...W RW RW RW RW RW RW RW RW RW RW RW RW RW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Reserved IRESET IDLLRS T R W RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit field Function Number Name 31 2 Reserved Reserved Writes are ignored Reads will return a 0 at all times 1 IRESET Control IRESET and IUSRRST...

Page 152: ...RT1 Soft Reset Reset the UART1 macro by writing 1 to this bit Set a 0 in this bit field during reset release 0 No Soft Reset initial value 1 Soft Reset 24 SRST0_24 UART0 Soft Reset Reset the UART0 macro by writing 1 to this bit Set a 0 in this bit field during reset release 0 No Soft Reset initial value 1 Soft Reset 23 17 Reserved Reserved Writes are ignored Reads will return a 0 at all times 16 S...

Page 153: ...t release 0 No Soft Reset initial value 1 Soft Reset 2 SRST0_2 GDC CAP1 Soft Reset Reset the GDC CAP1 macro by writing 1 to this bit Set a 0 in this bit field during reset release 0 No Soft Reset initial value 1 Soft Reset 1 SRST0_1 GDC CAP0 Soft Reset Reset the GDC CAP0 macro by writing 1 to this bit Set a 0 in this bit field during reset release 0 No Soft Reset initial value 1 Soft Reset 0 SRST0...

Page 154: ...Name 31 SRST1_31 GPIO Soft Reset Reset the GPIO macro by writing 1 to this bit Set a 0 in this bit field during reset release 0 No Soft Reset initial value 1 Soft Reset 30 SRST1_30 AXI Soft Reset Do the output of reset to AXI macro by writing 1 to this bit Set a 0 in this bit field during reset release 0 No Soft Reset initial value 1 Soft Reset 29 SRST1_29 MediaLB Soft Reset Do the output of reset...

Page 155: ...eserved 18 SRST1_18 UART5 Soft Reset Reset the UART5 macro by writing 1 to this bit Set a 0 in this bit field during reset release 0 No Soft Reset initial value 1 Soft Reset 17 SRST1_17 UART4 Soft Reset Reset the UART4 macro by writing 1 to this bit Set a 0 in this bit field during reset release 0 No Soft Reset initial value 1 Soft Reset 16 SRST1_16 UART3 Soft Reset Reset the UART3 macro by writin...

Page 156: ...set Reset the SPI macro by writing 1 to this bit Set a 0 in this bit field during reset release 0 No Soft Reset initial value 1 Soft Reset 8 7 Reserved 6 SRST1_6 I2S_0 Soft Reset Reset the I2S_0 macro by writing 1 to this bit Set a 0 in this bit field during reset release 0 No Soft Reset initial value 1 Soft Reset 5 SRST1_5 MBUS2AXI Cap Reset the MBUS2AXI Cap macro by writing 1 to this bit Set a 0...

Page 157: ...ister 2 for macro CMSR2 Address FFF2_2000 F8h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Reserved R W R R R R W R W R W R W R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Reserv ed SRST2_14 SRST2_13 SRST2_12 SRST2_11 SRST2_10 SRST2_9 SRST2_8 SRST2_7 SRST2_6 SRST2_5 SRST2_4 SRST2_3 SRST2_2 SRST2_1 SRST2_...

Page 158: ...Xch0 Soft Reset Reset the APIX ch0 incl PHY Ashell RegIf macro by writing 1 to this bit Set a 0 in this bit field during reset release 0 No Soft Reset initial value 1 Soft Reset 9 SRST2_9 ADC Soft Reset Reset the ADC macro by writing 1 to this bit Set a 0 in this bit field during reset release 0 No Soft Reset initial value 1 Soft Reset 8 SRST2_8 PWM_7 Soft Reset Reset the PWM_7 macro by writing 1 ...

Page 159: ...eset the PWM_2 macro by writing 1 to this bit Set a 0 in this bit field during reset release 0 No Soft Reset initial value 1 Soft Reset 2 SRST2_2 I2C_1 Soft Reset Reset the I2C_1 macro by writing 1 to this bit Set a 0 in this bit field during reset release 0 No Soft Reset initial value 1 Soft Reset 1 SRST2_1 HOST_SPI Soft Reset Reset the HOST_SPI macro by writing 1 to this bit Set a 0 in this bit ...

Page 160: ...power on reset 8 2 Features The RBC has the following features Remap control register INITRAM signal control register VINITHI signal control register 8 3 Block Diagram Figure 8 1 shows the RBC block diagram RBC Remap control register APB signals REMAP INITRAM control register INITRAM VINITHI control register VINITHI from pin VINITHI CRSTn from CRG HRESETn from CRG to BusMatrix to ARM926EJ S core t...

Page 161: ...s 8 5 1 Register list The RBC is controlled by the registers shown in Table 8 2 Table 8 2 RBC register list Address Register name Abbreviation Description Base Offset FFFE_6000H 00H Reserved Reserved area access prohibited 04H Remap control register RBREMAP Remap state control 08H VINITHI control register A RBVIHA VINITHI output signal control 0CH INITRAM control register A RBITRA INITRAM output s...

Page 162: ... 12 11 10 9 8 7 6 5 4 3 2 1 0 Name R W Initial value Meaning of item and sign Address Address base address offset address of the register Bit Bit number of the register Name Bit field name of the register R W Attribution of read write of each bit field R0 Read value is always 0 R1 Read value is always 1 W0 Write value is always 0 and write access of 1 is ignored W1 Write value is always 1 and writ...

Page 163: ... W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Reserved REM AP R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit field Description No Name 31 1 Reserved Reserved bit 0 REMAP Remap state is controlled When a write operat...

Page 164: ...ess GPR0 FFFE_6000H 08H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Reserved R W R R R R R R R R R R R R R R R R Initial value Determined by input level of external pin VINITHI Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Reserved VIHA R W R R R R R R R R R R R R R R R R W Initial value Determined by input level of external pin VINITHI Bit field Description No Name 31 1 Reserved Res...

Page 165: ...H 0CH Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Reserved R W R R R R R R R R R R R R R R R R Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Reserved ITRA R W R R R R R R R R R R R R R R R R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit field Description No Name 31 1 Reserved Reserved bits Write access is ignored Read value of these...

Page 166: ... to the built in boot ROM at power on and the system starts from it Using the remap control the allocated area is changed to the built in SRAM_1 memory allowing the built in vector table to be effectively overwritten 8 6 3 VINITHI control The ARM926EJ S core has a VINITHI signal which determines the exception vector address When low at reset the exception vector is located at 00000000H When the si...

Page 167: ...8 8 MB86R02 Jade D Hardware Manual V1 64 ...

Page 168: ... enables a reboot operation from ITCM Refer to the Technical reference manual of the ARM9 core provided by ARM Ltd for details of the INITRAM signal The RBITRA register is initialized to 0 by CRSTn however it is not reset by HRESETn This means a reboot operation from ITCM can be executed at software reset if the exception vector table is copied to ITCM before a software reset ...

Page 169: ... 0 18 When the IRQ interrupt is asserted to the ARM core the address of the interrupt vector table corresponding to the IRQ interrupt factor is generated during the register and displayed The IRQ interrupt handler should refer from 0 18 to the vector table of the expansion that was able to be certained further There is FIQ by the source and is no preference circuit for one For the interrupt contro...

Page 170: ...core as an interrupt of either IRQ 0000_0018H or FIQ 0000_001CH Table 9 1 Exception vectors defined by ARM926EJ S Exception factor Mode Vector address Reset SVC 0000_0000H Undefined instruction UND 0000_0004H Software interrupt SVC 0000_0008H Prefetch abort memory fault at instruction fetch Abort 0000_000CH Data abort memory fault at data access Abort 0000_0010H Reserved 0000_0014H IRQ usually int...

Page 171: ...H ICR10 48H 0000_0048H IRQ11 external interrupt 1 11 0BH ICR11 4CH 0000_004CH IRQ12 external interrupt 2 12 0CH ICR12 50H 0000_0050H IRQ13 external interrupt 3 13 0DH ICR13 54H 0000_0054H IRQ14 timer ch 0 interrupt 14 0EH ICR14 58H 0000_0058H IRQ15 timer ch 1 interrupt 15 0FH ICR15 5CH 0000_005CH IRQ16 DMAC ch 0 interrupt 16 10H ICR16 60H 0000_0060H IRQ17 DMAC ch 1 interrupt 17 11H ICR17 64H 0000_...

Page 172: ...errupt 11 0BH ICR11 4CH 0000_014CH IRQ12 I2C ch 1 interrupt 12 0CH ICR12 50H 0000_0150H IRQ13 PWM ch 0 interrupt 13 0DH ICR13 54H 0000_0154H IRQ14 PWM ch 1 interrupt 14 0EH ICR14 58H 0000_0158H IRQ15 UART ch 2 interrupt 15 0FH ICR15 5CH 0000_015CH IRQ16 UART ch 3 interrupt 16 10H ICR16 60H 0000_0160H IRQ17 UART ch 4 interrupt 17 11H ICR17 64H 0000_0164H IRQ18 UART ch 5 interrupt 18 12H ICR18 68H 0...

Page 173: ...nd ready 12 0CH ICR12 50H 0000_0250H IRQ13 RHlite Ch0 inbound ready 13 0DH ICR13 54H 0000_0254H IRQ14 RHlite Ch0 link error 14 0EH ICR14 58H 0000_0258H IRQ15 RHlite Ch0 FIFO error 15 0FH ICR15 5CH 0000_025CH IRQ16 RHlite Ch1 outbound ready 16 10H ICR16 60H 0000_0260H IRQ17 RHlite Ch1 inbound ready 17 11H ICR17 64H 0000_0264H IRQ18 RHlite Ch1 link error 18 12H ICR18 68H 0000_0268H IRQ19 RHlite Ch1 ...

Page 174: ...6R02 Jade D Hardware Manual V1 64 9 3 3 Interrupt request connection diagram Details of the interrupt request signal connection are shown in Figure 9 1 Figure 9 1 Connection diagram of interrupt request signal ...

Page 175: ...QF IRQM DICR1 0 FIQ Compare Level determination IRQ vector generation Display of accepted ICR level IRQ assertion flag Interrupt factor 00 FIQ Cancellation of STOP SLEEP mode IRQTEST IRQ interrupt control section HRCL Compare Bus request cancel request Bus request cancel request Timing control FIQTEST Interrupt factor 29 Figure 9 2 Block diagram of IRC ...

Page 176: ... V1 64 9 5 Register It explains the register of IRC 9 5 1 Register list The list of the register of IRC0 is shown in Table 9 5 The list of the register of IRC1 is shown in Table 9 6 The list of the register of IRC2 is shown in Table 9 7 ...

Page 177: ...he IRQ2 interrupt is set unused and access prohibited 3CH Interrupt control register 3 ICR03 The level of the IRQ3 interrupt is set unused and access prohibited 40H Interrupt control register 4 ICR04 The level of the IRQ4 interrupt is set unused and access prohibited 44H Interrupt control register 5 ICR05 The level of the IRQ5 interrupt is set IRC2 interrupt 48H Interrupt control register 6 ICR06 ...

Page 178: ... set DMAC ch 7 interrupt 90H Interrupt control register 24 ICR24 The level of the IRQ24 interrupt is set UART ch 0 interrupt 94H Interrupt control register 25 ICR25 The level of the IRQ25 interrupt is set UART ch 1 interrupt 98H Interrupt control register 26 ICR26 The level of the IRQ26 interrupt is set unused and access prohibited 9CH Interrupt control register 27 ICR27 The level of the IRQ27 int...

Page 179: ... register 3 ICR03 The level of the IRQ3 interrupt is set CAN ch 1 interrupt 40H Interrupt control register 4 ICR04 The level of the IRQ4 interrupt is set SD I F interrupt 44H Interrupt control register 5 ICR05 The level of the IRQ5 interrupt is set unused and access prohibited 48H Interrupt control register ICR06 The level of the IRQ6 interrupt is set I2S ch 0 interrupt 4CH Interrupt control regis...

Page 180: ...vel said to be valid from the ARM core is set 0CH ICR monitoring register ICRMN The interrupt level of a current IRQ interrupt source is displayed 10H Holding request cancellation level register HRCL The holding request cancellation level is set 14H Delay interrupt control register DICR The delay interrupt for the task switch is controlled 18H Reserved It is a reserved area access prohibited 1CH T...

Page 181: ...er 21 ICR21 The level of the IRQ21 RHlite Ch1 event 127 0 88H Interrupt control register 22 ICR22 RESERVED 8CH Interrupt control register 23 ICR23 RESERVED 90H Interrupt control register 24 ICR24 RESERVED 94H Interrupt control register 25 ICR25 RESERVED 98H Interrupt control register 26 ICR26 RESERVED 9CH Interrupt control register 27 ICR27 RESERVED A0H Interrupt control register 28 ICR28 RESERVED...

Page 182: ...ems and sign Address Address shows the address Base address Offset address of the register Bit Bit shows bit number of the register Name Name shows bit field name of the register R W R W shows the read write attribute of each bit field R0 The read value is always 0 R1 The read value is always 1 W0 The write value is always 0 If 1 is written it is ignored W1 The write value is always 1 If 0 is writ...

Page 183: ...8 27 26 25 24 23 22 21 20 19 18 17 16 Name R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Initial value X X X X X X X X X X X X X X X X Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name IRQF R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Initial value X X X X X X X X X X X X X X X 0 Bit field Explanation Number Name 31 1 It is an unused bit The write access i...

Page 184: ...Q interrupt 0 The assert of IRQ can certain the mask 1 The assert of IRQ is valid This bit is initialized by reset by 0 9 5 4 Interrupt level mask register ILM The ILM register sets the interrupt level said to be valid from the ARM core The interrupt controller notifies the ARM core the IRQ interrupt when the IRQ interrupt source is larger than the set value of this register Interrupt level of ICR...

Page 185: ...t is an unused bit The write access is ignored The read value of these bits is undefined 3 0 ILM3 0 These bits are used to set the IRQ interrupt level Level value range is from 0000B or less to 1111B or more The IRQ interrupt doesn t occur These bits are initialized by reset by 1111B ...

Page 186: ...ed by the source that sets the IRQF bit When the IRQF bit is not made 1 the register value is not defined Address IRC0 FFFF_FE00H or FFFE_8000H 0CH IRC1 FFFB_0000H 0CH IRC2 FFFB_1000H 0CH Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Initial value X X X X X X X X X X X X X X X X Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

Page 187: ...ion Number Name 31 4 It is an unused bit The write access is ignored The read value of these bits is undefined 3 0 HRCL3 0 Set the holding request cancellation level These bits are used to set the IRQ interrupt level to issue the holding request cancellation demand to bus masters other than ARM and TIC The bus request cancellation demand is issued when there is a high interrupt from the IRQ interr...

Page 188: ... W R W R W R W R W R W R W R W R W R W R W R W R W Initial value X X X X X X X X X X X X X X X X Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name DLYI R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Initial value X X X X X X X X X X X X X X X 0 Bit field Explanation Number Name 31 1 It is an unused bit The write access is ignored The read value of these bits is undefined 0 DLYI T...

Page 189: ...TBR29 TBR28 TBR27 TBR26 TBR25 TBR24 TBR23 TBR22 TBR21 TBR20 TBR19 TBR18 TBR17 TBR16 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name TBR15 TBR14 TBR13 TBR12 TBR11 TBR10 TBR9 TBR8 Zero Zero Zero Zero Zero Zero Zero Zero R W R W R W R W R W R W R W R W R W R R R R R R R R Initial value 0 0...

Page 190: ...Bit field Explanation Number Name 31 0 VCT31 0 Display the interrupt vector table to the interrupt source that should be processed The displayed vector value is a value that the offset value of each interrupt factor was added to the upper address value set depending on the TBR register Refer to Table 9 2 Expansion IRQ interrupt vectors of IRC0 and Table 9 3 Expansion IRQ interrupt vector of IRC1 f...

Page 191: ...ST21 ITST20 ITST19 ITST18 ITST19 ITST36 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name ITST15 ITST14 ITST13 ITST12 ITST11 ITST10 ITST9 ITST8 ITST7 ITST6 ITST5 ITST4 ITST3 ITST2 ITST1 ITST0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0...

Page 192: ...al value X X X X X X X X X X X X X X 0 0 Bit field Explanation Number Name 31 2 It is an unused bit The write access is ignored The read value of these bits is undefined 1 ITEST It is a control bit to test interrupt controller s IRQ interrupt function 0 The interrupt is not generated with IRQTEST and the FIQTEST register 1 The interrupt is generated with the ITST bit of the IRQTEST register and th...

Page 193: ...FFF_FE00H or FFFE_8000H 30H FFFF_FE00H or FFFE_8000H ACH IRC1 FFFB_0000H 30H FFFB_0000H ACH IRC2 FFFB_1000H 30H FFFB_1000H ACH Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Initial value X X X X X X X X X X X X X X X X Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name ICR3 ICR2 ICR1 ICR0 R W R W R W R W R W R W R W R W R W...

Page 194: ...h interrupt source Level value range is lowest from height 0000B 1111B ICR3 ICR3 ICR1 ICR0 Interrupt level 0 0 0 0 The highest level that can be set 0 0 0 1 height 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 lowest 1 1 1 1 Cannot the interrupt These bits are initialized by reset by 1111B ...

Page 195: ...rupt vector address of IRQ24 The interrupt handler of IRQ24 diverges by this branch instruction PC It is necessary to dispose all interrupt handlers within 32MB of the expansion interrupt vector table when the branch instruction is used Use loading instruction LDR PC PC _xxx instead of the branch instruction if the interrupt handler cannot dispose it within 32MB LDR PC PC _0x200 00000018H IRQ24 in...

Page 196: ...ble the interruption reception IRQ request 2 The first interrupt return process Do the same interrupt return process as the second to the first interruption The second interruption process Do the same interrupt process as the first to the second interruption The second interruption return process 1 Set I bit of the CPSR register and disable the interruption 2 Restore the value of SPSR_irq saved in...

Page 197: ... It is included in the core The IRQ interrupt is made valid enable Move to the corresponding interrupt handler when IRQ interrupt that is higher than a current IRQ source occurs Main routine for this interrupt factor MRS R2 CPSR ORR R2 R2 1_Bit MSR CPSR_c R2 Set I bit of the CPSR register It is included in the core Make the IRQ interrupt invalidity disable LDR R0 ILM LDMFD SP R1 R2 MSR SPSR_cxsf R...

Page 198: ... FIQ source The factor occurs in the macro even if the FIQ factor is asserted and the return doesn t occur when masking alleged This is because the interrupt is not transmitted by the interrupt controller Note of return by IRQ factor The factor occurs in the macro even if the FIQ factor is asserted and the return doesn t occur when masking alleged This is because the interrupt is not transmitted b...

Page 199: ...e when the code interrupt handler of which it is valid is the interrupt in the ARM core again immediately after 0 was writed to IRQF is written the ARM core has the possibility of entering the IRQ mode again by mistake by IRQX before it is cleared This has the possibility of occurring when the clock frequency in the ARM core is especially faster than the frequency of IRC To evade this problem add ...

Page 200: ...well as external interrupt request input to external pin of INT_A 3 INT_A 0 H level L level rising edge and falling edge are selectable as detected input request level 10 2Feature EXIRC has following features Operating as bus slave of AMBA APB 4 channels of external interrupt control 4 input request level selections H level L level Rising edge Falling edge Utilization of external interrupt as retu...

Page 201: ...ock diagram of EXIRC Table 10 1 shows block function included in EXIRC Table 10 1 Block function included in EXIRC Block Function EI_ENABLE Enabling external interrupt request for interrupt controller IRC0 EI_LEVEL Setting input request level H level L level rising edge falling edge EI_REQUEST Synchronizing and maintaining interrupt request EI_DOUT Generating data for reading 10 4Supply clock APB ...

Page 202: ...Address Register Abbreviation Description Base Offset FFFE_4000H 00H External interrupt enable register EIENB Enable control of external interrupt request output 04H External interrupt request register EIREQ Clear function of external interrupt display and interrupt request 08H External interrupt level register EILVL Selection of input request level detection of external interrupt ...

Page 203: ...t 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name R W Initial value Meaning of item and sign Address Address base address offset address of the register Bit Bit number of the register Name Bit field name of the register R W Attribution of read write of each bit field R0 Read value is always 0 R1 Read value is always 1 W0 Write value is always 0 and write access of 1 is ignored W1 Write value is always ...

Page 204: ...ue X X X X X X X X 0 0 0 0 0 0 0 0 Bit field Description No Name 31 8 Unused bit Write access is ignored Read value of these bits is undefined 7 4 Unused bit Write access is ignored Read value of these bits is always 0 3 0 ENB3 0 Masking external interrupt request output is controlled 0 External interrupt request is disabled 1 External interrupt request is enabled The interrupt request output corr...

Page 205: ...ess is ignored Read value of these bits is undefined 7 4 Unused bit Write access is ignored Read value of these bits is always 0 3 0 REQ3 0 External interrupt request is indicated and cleared 0 At reading There is no external interrupt request At writing External interrupt request is cleared 1 At reading There is external interrupt request At writing External interrupt request invalid Read value o...

Page 206: ...R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Initial value X X X X X X X X 0 1 0 1 0 1 0 1 Bit field Description No Name 31 8 Unused bit Write access is ignored Read value of these bits is undefined 7 0 LVL3 1 0 LVL0 1 0 Input request level detection of external interrupt is selected 2 bit is allocated to each external interrupt channel This is initialized to 01B by reset LVL0 1 0 E...

Page 207: ...of external interrupt 10 7Operation procedure External interrupt register setting procedure is as followings 1 Disable EIENB register related bit 2 Set EILVL register related bit 3 Clear EIREQ register related bit 4 Enable EIENB register related bit EIENB register must be disabled to set register in the module moreover EIREQ register needs to be cleared before EIENB register is enabled This operat...

Page 208: ...32 bit is an option width of SRAM Flash 3 chip selections for SRAM Flash MEM_XCS 4 is for boot operation Parameter setting by individual chip selection for SRAM Flash Supporting NOR flash page access Supporting Bi endian 11 3Block diagram Figure 11 1 shows block diagram of external bus interface CCPB AHB Bus External Bus I F AHB I F Switcher MEM_RDY MEM_XCS 4 2 0 MEM_XRD MEM_EA 24 1 MEM_XWR 3 2 ME...

Page 209: ...d pin MEM_XRD O 1 Reading enabled MEM_XCS 4 O 1 Chip selection for boot operation MEM_XCS 2 O 1 Chip selection MEM_XCS 0 O 1 Chip selection MEM_ED 31 0 IO 32 Data bus Upper 16 bits are multiplexed pin MEM_RDY I 1 Ready input for low speed device 11 5Supply clock AHB clock is supplied to external bus interface Refer to 5 Clock reset generator CRG for frequency setting and control specification of t...

Page 210: ... asserted to L at least 2 cycles from 2 cycles before falling edge of MEM_XRD signal to actual falling edge For the writing operation the RDY signal should also be asserted to L at least 2 cycles from 2 cycles before falling edge of MEM_XWR signal to actual falling edge For accessing to device such as SRAM memory without using the MEM_RDY signal this bit should be set to 0 0 READY mode OFF initial...

Page 211: ... V1 64 Bit1 0 WDTH data width These bits specify data bit width of the connected device 0 8 bit initial value 1 16 bit 2 32 bit 3 Reserved 1 Initial value of data width to MEM_XCS 4 MPX_MODE_1 1 0 2 b01 or 2 b10 2 32 bit Others 1 16 bit ...

Page 212: ...s set the number of idle cycle after the write access When RDY bit is set to 1 specify 2 or more value 0 1 cycle initial value 15 16 cycles Bit27 24 WWEC Write Enable Cycle These bits set the number of write enable assertion cycle This setting also affects to MEM_XWR 3 0 When RDY bit is set to 1 the value should be 3 or more 4 cycles or more 0 1 cycle 5 6 cycles initial value 14 15 cycles 15 Reser...

Page 213: ...r of cycle specified by these bits only at the first read access The subsequent read access is executed according to the number of cycle set in the RACC MEM_XCS 0 2 4 and MEM_XRD are asserted simultaneously When other values than 0 are set to these bits specify 0 to RADC Read Address Setup Cycle 0 0 cycle initial value 15 15 cycles Bit7 4 RADC Read Address Setup cycle These bits set number of read...

Page 214: ...11 7 MB86R02 Jade D Hardware Manual V1 64 15 16 cycles initial value ...

Page 215: ...em When they are matched external bus interface accesses to MEM_XCS 4 2 0 signal 22 16 masks each address 26 20 Example ADDR 00001000 b MASK 0000011 b When the device is selected Internal bus address external interface address AD 0x10900000 Mask ADDR MASK 00001000 b AD 27 20 MASK 00001000 b Matched and this device is selected When the device is not selected Internal bus address external interface ...

Page 216: ...11 9 MB86R02 Jade D Hardware Manual V1 64 0000011 b 4MB 0111111 b 64MB 0000111 b 8MB 1111111 b 128MB ...

Page 217: ...0x0200_0000 0x11FF_FFFF are allocated by SRAM Flash interface in 256MB fixed area Define corresponding value to 27 20 part of the address ADDR address 27 20 Setting address of chip selecting area 0xFF 0x0FF0_0000 1 0xFE 0x0FE0_0000 1 0x21 0x0210_0000 1 0x20 0x0200_0000 1 0x1F 0x11F0_0000 2 0x1E 0x11E0_0000 2 0x01 0x1010_0000 2 0x00 0x1000_0000 2 1 Address becomes 31 28 0 0 at ADDR address 27 20 20...

Page 218: ...ue is undefined Bit3 Reserved Reserved bit Write 0 to these bits Their value is undefined Note Writing 1 to this bit is prohibited Bit2 SFION SRAM Flash error interrupt ON This bit validates interrupt at SRAM Flash error 0 OFF initial value 1 ON Bit1 Reserved Reserved bit Write 0 to these bits Their value is undefined Bit0 SFER SRAM Flash error This bit indicates that the area without mapping is a...

Page 219: ...2 MEM_EA 24 1 MEM_XCS 4 MEM_XRD MEM_XWR 0 MEM_ED 15 0 x16 NOR Flash A XCE XOE XWE DQ 15 0 MB86R02 x8 SRAM x8 SRAM MEM_ED 7 0 MEM_ED 15 8 MEM_EA 24 1 MEM_XCS 0 MEM_XRD MEM_XWR 1 0 MEM_ED 15 0 MEM_XCS 4 MEM_XWR 0 MEM_XWR 1 A CSn OEn WEn DQ 7 0 A CSn OEn WEn DQ 7 0 x16 NOR Flash A XCE XOE XWE DQ 15 0 MEM_XWR 0 MEM_ED 15 0 ...

Page 220: ...CC tRACC cycle tRADC Read address setup cycle tRADC tRACC Read access cycle tRADC tRIDLC tRIDLC Read idle cycle Word write access to 16 bit width SRAM NOR Flash 01 X D01 MEM_EA 24 1 00 D00 X MEM_ED 15 0 MEM_XRD MEM_XWR 1 0 MEM_XCS 4 2 0 Internal clock MEM_RDY tWACC tWADC Write address setup cycle tWADC tWACC Write access cycle tWADC tWIDLC tWWEC Write enable cycle tWWEC X tWWEC tWIDLC Write idle c...

Page 221: ...cle tRIDLC Wait cycle tRIDLC Read idle cycle Figure 11 2 Half word read access to 16 bit width low speed device X MEM_EA 24 1 00 D00 X MEM_ED 15 0 MEM_XRD MEM_XWR 1 0 MEM_XCS 4 2 0 Internal clock MEM_RDY tWACC Wait cycle tWADC Write address setup cycle tWADC Min 2 cycles tWACC Write access cycle tWIDLC Wait cycle tWWEC Write enable cycle tWWEC X tWIDLC Write idle cycle 1 cycle 1 cycle Figure 11 3 ...

Page 222: ...ait2 cycle tRIDLC Read idle cycle Figure 11 4 Word read access to 16bit low speed device 01 X D01 MEM_EA 24 1 00 D00 X MEM_ED 15 0 MEM_XRD MEM_XWR 1 0 MEM_XCS 4 2 0 Internal clock MEM_RDY tWACC Wait1 cycle tWACC Wait2 cycle tWADC write address setup cycle tWADC Min 2 cycles tWACC Write access cycle tWADC Min 2 cycles tWIDLC Wait1 cycle Wait2 cycle tWWEC Write enable cycle tWWEC X tWWEC tWIDLC Writ...

Page 223: ...read of 16 bit NOR Flash 02 MEM_EA 24 1 00 D00 X MEM_ED 15 0 MEM_XRD MEM_XWR 1 0 MEM_XCS 4 2 0 Internal clock MEM_RDY tFRADC First read access cycle tRACC Read access cycle tFRADC X 04 06 08 0A tRACC tRACC D02 D04 D06 D08 D0A tRACC tRACC tRACC tRACC ...

Page 224: ...control during writing operation for external bus interface only necessary data is output 11 9 2 Low speed device interface function The external bus interface has interface function with low speed device and MEM_RDY pin which are used by connecting RDY signal to MEM_RDY pin of this LSI MEM_RDY pin is available only when wait state is at L and ready state is at H RDY signal at reading should be as...

Page 225: ...ATA 31 16 not active 00 1 0 MEM_ED 15 0 H DATA 15 0 11 00 0 2 MEM_ED 31 16 H DATA 31 16 00 11 0 0 MEM_ED 7 0 H DATA 7 0 not active 10 0 1 MEM_ED 7 0 H DATA 15 8 not active 10 0 2 MEM_ED 7 0 H DATA 23 16 not active 10 1 3 MEM_ED 7 0 H DATA 31 24 not active 10 1 0 MEM_ED 7 0 H DATA 7 0 not active 10 0 1 MEM_ED 15 8 H DATA 15 8 not active 01 0 2 MEM_ED 7 0 H DATA 23 16 not active 10 1 3 MEM_ED 15 8 H...

Page 226: ...TA 23 16 not active 01 0 2 MEM_ED 15 8 H DATA 15 8 not active 01 1 3 MEM_ED 15 8 H DATA 7 0 not active 01 1 0 MEM_ED 15 8 H DATA 31 24 not active 01 0 1 MEM_ED 7 0 H DATA 23 16 not active 10 0 2 MEM_ED 15 8 H DATA 15 8 not active 01 1 3 MEM_ED 7 0 H DATA 7 0 not active 10 1 32bit prohibited 0 MEM_ED 15 8 H DATA 31 24 not active 01 0 1 MEM_ED 15 8 H DATA 23 16 not active 01 0 2 MEM_ED 15 8 H DATA 1...

Page 227: ...s Operation as bus slave of AMBA AHB 2pcs of embedded SRAM are accessible from different 2 AHB masters simultaneously 32KB of SRAM is equipped to each embedded SRAM 12 3Block diagram Figure 12 1 shows block diagram of embedded SRAM AHB bus Built in SRAM_1 32KB Built in SRAM_0 32KB Figure 12 1 Block diagram of embedded SRAM 12 4Supply clock AHB clock is supplied to embedded SRAM Refer to 5 Clock re...

Page 228: ...ing read write transactions to internal FIFO by slave function of AHB IF b Internal FIFO composition a Address FIFO Depth 8 28 controllable with register setting b Write data FIFO Depth 52 c Read data FIFO Depth 62 d Read control FIFO Depth 28 c DRAM IF c 512M bit 256M bit DDR2SDRAM SSTL18 2pcs recommended or 1pc DDR2 400 533 667 800 in compliance with JESD79 2C is used as DDR2 400 in addition SDR...

Page 229: ...B IF Register Figure 13 1 Block diagram of DDR2 controller DDR2C Block Function AHB IF Slave function of AHB IF Control register AXI IF Slave function of AXI IF FIFO control function FIFO Address Write Data Read Control Read Data storage FIFO DRAM IF DDRIF macro control function SDRAM IF control function DDRIF macro Connection between DRAM IF module and IO Read data s importing phase adjustment Bu...

Page 230: ...0H 1FH Reserved Access prohibited 20H DRAM CTRL FIFO Register DRCF FIFO control register 22H 2FH Reserved Access prohibited 30H AXI Setting DRASR AXI operation setting register 32H 4FH Reserved Access prohibited 50H DRAM IF MACRO SETTING DLL Register DRIMSD DDRIFmacro setting register 52H 5FH Reserved Access prohibited 60H DRAM ODT SETTING Register DROS ODT setting register 62H 63H Reserved Access...

Page 231: ...it 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name R W Initial value Meaning of item and sign Address Address base address offset address of the register Bit Bit number of the register Name Bit field name of the register R W Attribution of read write of each bit field R0 Read value is always 0 R1 Read value is always 1 W0 Write value is always 0 and write access of 1 is ignored W1 Write value is always...

Page 232: ...ccess request to DDR is able to be judged by DDRBSY bit 2 When DRINI bit is 1 do not access to data from AXI When data access is requested in the state of DRINI 1 DDR2 controller may keep occupying the AXI bus Moreover the data requested from AXI may be destroyed 14 CKEN This is CKE control signal to DDR Normal operation DRINI 0 CKE output always becomes 1 Initialization mode DRINI 1 CKE output be...

Page 233: ...t to DRAM Writing 1 to this bit outputs setting condition of DRAM initialization command register 1 2 to DRAM during 1ck period of time Note When DRCMD bit does not issue command in the initialization mode the state becomes NOP or DSEL to DRAM Only when CMDBSY bit 1 is 0 1 is able to be written to this bit ...

Page 234: ...A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRAM initialization method All DRAM is initialized by CPU DDR2 controller is structured that each signal conductor necessary for the DRAM setting can be driven by the register value in the initialization mode Set certain value to th...

Page 235: ...on mode of DRAM control core is set 11 DRAM control core operates in the DDR2SDRAM mode Others Reserved setting prohibited 13 Bus16 This specifies bus width of DRAM connected to external part 0 32 bit 1 16 bit Remark Use DQ 15 0 DQS0 1 and DM0 1 See the pin specifications for process of unused DQ 31 16 DQS2 3 and DM2 3 12 10 Reserved Reserved bits Write access is ignored 9 8 BankRange Bank address...

Page 236: ...erved bit Write access is ignored 10 8 AL Additive latency is set This module operates with AL 0 and it should also be set to DRAM 7 Reserved Reserved bit Write access is ignored 6 4 CL CAS latency is specified 011 CL 3 fixed Others Reserved setting prohibited DRAM setting should also have the same as this register s 3 Reserved Reserved bit Write access is ignored 2 0 BL Burst length is specified ...

Page 237: ...15 Reserved Reserved bit Write access is ignored 14 12 TRCD RAS to CAS delay time rRCD Active to read or write command delay Bit 14 12 Delay time number of clock 000 Reserved Setting prohibited 001 010 2 011 3 100 4 101 5 110 6 111 7 Initial value 11 Reserved Reserved bit Write access is ignored 10 8 TRAS RAS active time rRAS Active to precharge command Bit 10 8 Delay time number of clock 000 Rese...

Page 238: ...nitial value 3 0 TRC RAS cycle time tRC Active to active Auto refresh command time Bit 3 0 Delay time number of clock 0000 Reserved Setting prohibited 0001 0010 0011 0100 0101 0110 8 0111 9 1000 10 Note 1 1001 11 1010 12 1011 13 1100 14 1101 15 1110 16 1111 17 Initial value Note 1 When 10 or less value is set writing to DRAM is performed with tRAS 11 For ACT command interval larger value of either...

Page 239: ...gnored 11 8 TRFC Auto refresh command period tRFC Auto refresh to active Auto refresh command time Bit 11 8 Cycle time number of clock 0000 4 0001 5 0010 6 0011 7 0100 8 0101 9 0110 10 0111 11 1000 12 1001 13 1010 14 1011 15 Initial value 1100 16 1101 17 1110 18 1111 19 7 6 Reserved Reserved bits Write access is ignored 5 4 TRRD RAS to RAS bank active delay time tRRD Active bank A to active bank B...

Page 240: ...ription No Name 2 0 TWR Write recovery time tWR Write recovery time Write recovery time of DRAM is set in cycle Bit 2 0 Cycle time number of clock 000 Reserved setting prohibited 001 2 010 3 011 4 100 5 101 6 Initial value 110 Reserved setting prohibited 111 ...

Page 241: ... setting value needs to be applied such as after REF_CNT value change This bit does not need to be rewritten to 0 immediately after loaded because it is performed after detecting the bit change However this bit keeps the writing value If bit value is not 0 at executing load operation 1 should be written after writing 0 Although CNTLD is not used after REF_CNT change it operates with the changed RE...

Page 242: ...ult 1 Capture bandwidth is improved 14 5 Reserved Reserved bits Write access is ignored 4 0 FIFO_CNT FIFO FULL count This is number of stage setting of address FIFO FULL condition When picture flickers due to AXI access latency at using display and capture it is recovered by reducing number of FIFO stage and decreasing AXI bus latency Bit 4 0 Address FIFO number of stage 00H 01H Reserved setting p...

Page 243: ...X X X 0 Bit field Description No Name 15 1 Reserved Reserved bits Write access is ignored 0 CACHE CACHE On Off of cash operation at reading are performed 0 Cache off initial value 1 Cache on When single reading continuously occurs in a single access 16 byte to DRAM reading operation from AXI is enabled by the cached data in AXI module instead of accessing to DRAM However cache is cleared in the fo...

Page 244: ... of ISFT_3 2 0 110 Initial value 101 Normal operation setting value set to 101 at DRAM initialization Others Reserved setting prohibited 11 Reserved Reserved bit Write access is ignored 10 8 ISFT_2 2 0 Value of ISFT_2 2 0 110 Initial value 101 Normal operation setting value set to 101 at DRAM initialization Others Reserved setting prohibited 7 Reserved Reserved bit Write access is ignored 6 4 ISFT...

Page 245: ...nal part Address F300_0000H 60H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name ODT 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Initial value X X X X X X X X X X X X X X X 0 Bit field Description No Name 15 1 Reserved Reserved bits Write access is ignored 0 ODT0 This is the value of external output pin ODTCONT Initial value is 0 ...

Page 246: ... IO buffer s ODTON is always 0 1 This should be set to use ODT of IO buffer ODTON is set to off in the following case To adjust OCD 3 ZSELP This becomes ZSELP value of the IO buffer and it is ODT resistance setting of DQSP s IO 0 150Ω or 100Ω initial value 1 75Ω or 50Ω 2 ODTONP This is ODT setting of DQS s IO and controls ODTONP of the IO buffer Initial value is 0 0 IO buffer s ODTON is always 0 1...

Page 247: ...ed bits Write access is ignored 4 AFORCE This is control bit to switch IO driver s A input and 1 is set at impedance adjustment Initial value is 0 When this bit is 1 ADRV bit value of bit 3 is added to driver input A of IO buffer Be sure to set 0 at the normal operation 3 ADRV This bit combines with AFORCE of bit 4 to use When AFORCE is 1 this bit value becomes IO driver s A input When AFORCE is 0...

Page 248: ... X X X X X X X 0 0 0 Bit field Description No Name 15 3 Reserved Reserved bits Write access is ignored 2 SUSPD SUSPD setting of IO buffer When SSEL 1 this bit value is supplied to SUSPD of each IO buffer 1 SUSPR SUSPR setting of IO buffer When SSEL 1 this bit value is supplied to SUSPR of each IO buffer 0 SSEL This is selection bit whether to use value of bit1 or bit2 for SUSPR SUSPD or to control...

Page 249: ... value 7 OCOMPPPOL This sets to detect either 0 1 or 1 0 of OCOCMPP value as valid at bias adjustment operation 0 0 1 is valid initial value 1 1 0 is valid 6 4 Reserved Reserved bits Write access is ignored 3 2 IAVSET Average number of times of bias adjustment is specified Adjustment is performed for predetermined number of times to output the average value to ODT of the I O cell 00 32 times initi...

Page 250: ...W R W R W R W R W R W R W R W Initial value X X X X X X X X X X X X X X X 0 Bit field Description No Name 15 1 Reserved Reserved bits Write access is ignored 0 AUTO This sets whether to use ODT auto setting value mode When it is set the average value calculated with auto adjustment of the bias is used to ODT value of the I O cell 0 The ODT auto setting value mode is not used 1 The ODT auto setting...

Page 251: ...CD2 register 68H is set to 1 Bit 1 of IO buffer setting OCD2 register 68H is set to 0 Remark Monitor value is valid only at OCD adjustment 13 6 20 IO monitor register 2 DRIMR2 This is input level monitor of IO buffer which is used for impedance adjustment of OCD Address F300_0000H 92H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name DQX 31 16 R W R Initial value X X X X X X X X X X X X X X X X Bit f...

Page 252: ... is set to 1 Bit 1 of IO buffer setting OCD2 register 68H is set to 0 Remark Monitor value is valid only at OCD adjustment 13 6 22 IO monitor register 4 DRIMR4 This is input level monitor of IO buffer which is used for impedance adjustment of OCD Address F300_0000H 96H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name DMX 15 0 R W R Initial value X X X X X X X X X X X X X X X X Bit field Description ...

Page 253: ...VN1 This register sets DRVN value of DQ 7 0 DQS0 and DM0 3 0 DRVP1 This register sets DRVP value of DQ 7 0 DQS0 and DM0 13 6 24 OCD impedance setting register 2 DROISR2 This register sets impedance adjustment value Address F300_0000H 9AH Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name DRVN4 DRVP4 DRVN3 DRVP3 R W R W R W R W R W Initial value 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 Bit field Description No ...

Page 254: ...Procedure for more detail of initialization sequence Figure 13 2 DDR2SDRAM initialization time chart IRESET 5 DDRIF Macro RESET XRST CHIP RESET IUSRRST 5 DDRIF Macro RESET IDLLRST 5 DDRIF Macro DLL RESET MCKE DDR2 IF CKE 1 PLL lock up time or more 2 MCKP cycle 166MHz 6 ns 20cycle 120 ns MCKP DDR2 IF CLK MCS DDR2 IF XCS 3 DLL lock up time or more 79 us 4 Based on DDR2SDRAM spec ODTCONT DDR2 IF ODT ...

Page 255: ...e The figure below is a whole flow of the register setting procedure for initialization sequence Each number matches to the one in DDR2SDRAM initialization time chart shown in Figure 13 2 The procedure showing here is only the register setting relating to the DRAM initialization ...

Page 256: ...µs or more Wait 8 200 µs specification of DDR2SDRAM or more Wait 9 MCKE on Write 003F to DRIC1 register offset 02h Write 0000 to DRIC2 register offset 04h Write C124 to DRCA register offset 06h Write C000 to DRIC register offset 00h 10 SDRAM initialization 11 OCD adjustment and ODT setting CHIP side 12 Shift to ODTCONT on SDRAM side and DDR2C normal operation mode Write 0001 to DROS register offse...

Page 257: ...nitialization setting procedure at DRAM initialization DDR2SDRAM initialization sequence s command contents to be issued may change depending on the memory specification connected to this chip For each command s issuing contents and DDR2C command issuing timing be sure to confirm memory spec in use to set properly ...

Page 258: ...001 to DRIC register offset 00h DDR2 IF Issue EMR 1 command Write 0000 to DRIC1 register offset 02h Write 0532 to DRIC2 register offset 04h Write C001 to DRIC register offset 00h DDR2 IF Issue MRS command Write 0017 to DRIC1 register offset 02h Write 0400 to DRIC2 register offset 04h Write C001 to DRIC register offset 00h DDR2 IF Issue PALL command Write 000F to DRIC1 register offset 02h Write 000...

Page 259: ...CM register offset 08h Write 3318 to DRCST1 register offset 0Ah Write 6E32 to DRCST2 register offset 0Ch Write 0141 to DRCR register offset 0Eh Write 0002 to DRCF register offset 20h Write 0001 to DRASR register offset 30h DDR2 IF timing setting tRCD tRAS tRP and DDR2 IF timing setting tRFC tRRD and tWR Refresh issued at DDR2C normal operation mode Command issuing interval setting the value is f A...

Page 260: ...o 1 DRVP1 2 3 4 Decrement to 0 F DRVN1 2 3 4 0 Read adjustment level of PMOS driver output impedance from DRIMR1 register Read DRIMR1 register offset 90h Read DRIMR2 register offset 92h Read DRIMR3 register offset 94h Read DRIMR4 register offset 96h Judge DRIMR1 4 all 1 Write 0X0X FXFX to DROISR1 register offset 98h Write 0X0X FXFX to DROISR2 register offset 9Ah Increment applied NMOS driver setti...

Page 261: ...15 8 DQX 15 8 1 DQSX 1 1 DMX 1 3 0 DRVP1 7 0 DQX 7 0 0 DQSX 0 0 DMX 0 Table 13 4 Correspondence table of DRVP3 4 and DRIMR2 3 4 registers DROISR1 register DRIMR2 register DRIMR3 register DRIMR4 register 11 8 DRVP4 15 8 DQX 31 24 3 DQSX 3 3 DMX 3 3 0 DRVP3 7 0 DQX 23 16 2 DQSX 2 2 DMX 2 Table 13 5 Correspondence table of DRVN1 2 and DRIMR1 3 4 registers DROISR2 register DRIMR1 register DRIMR3 regis...

Page 262: ...sts ODT of SSTL_18 IO moreover auto adjustment always operates during memory reading at normal operation Pin for ODT adjustment is MDQ 31 0 MDM 3 0 MDQSP 3 0 and MDQSN 3 0 Write 0001 to DROBS register offset 84h START Set to the mode using ODT auto setting value ODT auto adjustment on Set ODT to on 50Ω 100Ω 003F 75Ω 150Ω 0015 Write 0083 to DROABA register offset 70h Write 003F to DRIBSODT1 registe...

Page 263: ...quest signals to interrupt controller Timer clock prescaler unit 3 operation modes Free run mode Cycle timer mode One shot mode Using APB clock as base clock of the timer 14 3 Supply clock APB clock is supplied to timer Refer to 5 Clock Reset generator CRG for frequency setting and control specification of the clock 14 4 Specification Timer in MB86R02 uses ADKr2p0 AMBA design kit timer module of A...

Page 264: ...on DMA request selectable per channel Software request start up by register write Beat transfer 16 word FIFO shared by all channels Supports INCR INCR 4 8 16 and WRAP 4 8 16 Transfer modes Block transfer I2S check Limitations with I2S section Burst transfer not to I2S Demand transfer not to I2S Programmable 4 bit block register and 16 bit count register Supports 8 16 and 32 bit transfer widths Sup...

Page 265: ...15 2 MB86R02 Jade D Hardware Manual V1 64 15 3Block diagram Figure 15 1 shows a block diagram of the DMA Controller Figure 15 1 DMA Controller Block Diagram ...

Page 266: ...dmacRegister DMAC DMA configuration register controller HdmacFIFO DMAC 16 word FIFO 15 4Related pins MB86R02 s DMAC has the following DMA related pins which are shared with other functions To use the pins for DMA the external pins should be set to MPX_MODE_1 1 0 HL Pin Direction Qty Description DREQ 6 DREQ 7 I 2 DMA request pin which is connected as channel 7 of DMAC and channel 6 of external DREQ...

Page 267: ...A2 DMAC2 Destination address register DMAC ch3 FFFD0040 h DMACA3 DMAC3 configuration A register FFFD0044 h DMACB3 DMAC3 configuration B register FFFD0048 h DMACSA3 DMAC3 source address register FFFD004C h DMACDA3 DMAC3 Destination address register DMAC ch4 FFFD0050 h DMACA4 DMAC4 configuration A register FFFD0054 h DMACB4 DMAC4 configuration B register FFFD0058 h DMACSA4 DMAC4 source address regis...

Page 268: ...onfiguration register DMACR to 15 6 6 DMAC destination address register DMACDAx Address Base address Offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name R W Initial value Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name R W Initial value Meaning of item and sign Address Address base address offset address of the register Bit Bit number of the register Name Bit field name of the register ...

Page 269: ... occurs at BC 0 after completing transfer in BC unit Burst transfer There is no transfer gap Demand transfer Transfer gap occurs at TC TC 1 after completing 1 DMA transfer or at transfer request negotiation This bit can be used to reset all channels of Configuration register at a time during DMA transfer 30 DS DMA Stop This shows all channels of DMA transfer is stop 0 Release of disable halt setti...

Page 270: ...is not transferred until 4 b0000 is set If the value other than 4 b0000 is set during DMA transfer it is stopped at transfer gap Refer to DE bit description for the transfer gap These bits are used to stop DMA transfer without resetting each configuration register of all channels 0000 Stop release Other than 0000 Stop of channels 23 0 Reserved Reserved bits Write access is ignored Read value of th...

Page 271: ...nsfer is not performed until 1 is set to this bit If 0 is set to this bit during DMA transfer DMA stops at transfer gap which is regarded as forcible termination Refer to DMACR DE bits description for transfer gap This bit is able to use for resetting each configuration register of the channel during DMA transfer 0 This channel is disabled initial value 1 This channel is enabled 30 PB Pause Bit Th...

Page 272: ...all channels IS 4 0 Function 0 h Software request 1 h B h Invalid E h DREQ H active level or rising edge F h DREQ L active level or falling edge 10 h IDREQ 0 H active level or rising edge 11 h IDREQ 1 H active level or rising edge 12 h IDREQ 2 H active level or rising edge 13 h IDREQ 3 H active level or rising edge 14 h IDREQ 4 H active level or rising edge 15 h IDREQ 5 H active level or rising ed...

Page 273: ...eat transfer type is Normal Single or INCR When other types of beat fixed length burst and lap are set these bits are ignored In addition they are able to be read during DMA transfer After single source access and single destination access are properly completed normally BC bit is decremented for 1 Note These bits are settable even beat type bit BT 3 0 is INCR however read data of BC after startin...

Page 274: ...ld Description No Name 31 30 TT 1 0 Transfer Type These bits are used to specify transfer type Currently only 2 cycle transfer mode is available for DMAC TT 1 0 Function 0 h 2 cycle transfer initial value Other than 0 h Reserved 29 28 MS 1 0 Mode Select These bits are used to select transfer mode MS 1 0 Function 0 h Block transmission mode initial value 1 h Burst transmission mode 2 h Demand trans...

Page 275: ...s disabled initial value 1 h Reload function of source address is enabled 21 RD Reload Destination This bit is used to control reload function of destination address DMACDA 1 is set to this bit DMACDA is set to the initial value after DMA transfer 0 is set to this bit DMAC sets the next destination address to DMACDA after DMA transfer RD Function 0 h Reload function of destination address is disab...

Page 276: ... same time end code is displayed by the following priority High priority Reset Clear by 3 b000 writing Address overflow Demand stop Source access error Destination access error Low priority 15 12 SP 3 0 Source Protection These bits are used to control source protection HPROT at source access issues this value to AHB however it is not performed if source target does not equip protection function SP...

Page 277: ...ACSA 15 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit field Description No Name 31 0 DMACSA 31 0 DMAC Source Address These bits are used to specify source address to start DMA transfer and they are able to be read during DMA transfer When fixed address function DMACB FS is disabled these bits are incremented according to the...

Page 278: ...W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit field Description No Name 31 0 DMACDA 31 0 DMAC Destination Address These bits are used to specify destination address to start DMA transfer and they are able to be read during DMA transfer When fixed address function DMACB FD is disabled these bits are incremented according to the t...

Page 279: ... the DMAC from blocking the bus This transfer gap can be used to update the register settings e g disable interruption setting to the DMAC during DMA transfer Transfer request Three types of request are valid in this mode request by software external request DREQ and peripheral request IDREQ Software request Set 1 to DMACA ST and set 5 b00000 to DMACA IS External request Set 0 to DMACA ST and set ...

Page 280: ...ion IDEOP Basically DEOP IDEOP is asserted for 1 AHB clock HCLK cycle if the DMAC terminates DMA transfer properly or abnormally Abnormal DMA transfer includes the following cases Forced termination by DSTP IDSTP Forced termination by setting 1 b0 to DMACA EB Reception of an error response from the source destination 4 DSTP Data Stop IDSTP DSTP IDSTP are used to forcibly terminate DMA transfer and...

Page 281: ...P HDMAC OK Other master NONSEQ or SEQ READ or WRITE Other master NONSEQ or SEQ READ or WRITE Figure 15 2 Example of DEOP IDEOP exception operation DREQ IDREQ DACK IDACK DEOP IDEOP and DSTP IDSTP are not valid when DMA transfer is performed in software request mode Timing chart Figure 15 3 shows a block transfer as a timing chart ...

Page 282: ...HBUSREQ HGRANT HREADY HRESP HMASTER CPU HDMAC CPU HDMAC CPU OK SA DA SA DA SA DA SA DA HTRANS N N N N N N N N I I Data Data Data Data Data Data Data 0x00 0xA0 DMACA 19 16 0x0 0x1 BC 0x00 0x0 0x1 0x0 DMACA 15 0 0x0 0x1 TC 0x0 DMACSA DMACDA SA0 SA1 SA2 SA3 SA4 DA0 DA1 DA2 DA3 DA4 Break of transfer Data Figure 15 3 Block transfer for BC 0x1 and TC 0x1 ...

Page 283: ...es of the respective DMAC register DMACAx DMACA0 DMACA7 various offsets Each block matches one transfer request The selected DMAC transfer mode must be Block Transfer check the DMACBx registers Demand and burst transfer modes can not be used with I2S In order for DMA transfers to work with the I2S unit each transfer has to transmit receive as many words to from FIFO as there are valid entries When...

Page 284: ...MA transfer e g disable interruption setting are reflected after completing DMA transfer Transfer request Software request external DREQ and peripheral IDREQ requests are valid in this mode Software request Set 1 to DMACA ST and set 5 b00000 to DMACA IS External request Set 0 to DMACA ST and set 5 b01110 rising edge of transfer request or 5 b01111 falling edge of transfer request to DMACA IS Perip...

Page 285: ...ination access properly 3 DEOP IDEOP Basically DEOP IDEOP are asserted for 1 AHB clock HCLK cycle when the DMAC ends DMA transfer properly or abnormally Abnormal DMA transfer includes the following cases Forced termination by DSTP IDSTP Forced termination by setting 1 b0 to DMACA EB Reception of an error response from the source destination 4 DSTP IDSTP DSTP IDSTP are used to forcibly terminate DM...

Page 286: ...MAC HMASTER Control HREADY IDLE READ HRESP NOSEQ or SEQ READ or WRITE HDMAC OK Other master Other master NOSEQ or SEQ READ or WRITE Figure 15 4 Example of DEOP IDEOP exception operation DREQ IDREQ DACK IDACK DEOP IDEOP and DSTP IDSTP are not valid if DMA transfer is performed by software reset ...

Page 287: ...TE Control External trigger Software trigger DMACA 31 24 HWDATA HRDATA HBUSREQ HGRANT HREADY HRESP HMASTER CPU HDMAC CPU OK SA DA SA DA SA DA HTRANS N N N N N I N Data Data Data Data Data Data 0x00 0xA0 DMACA 19 16 0x0 0x1 BC 0x00 0x0 0x1 0x0 DMACA 15 0 0x0 0x1 TC 0x0 SA DA N N Data Data Figure 15 5 Burst transmission for BC 0x1 and TC 0x1 ...

Page 288: ...ly negates the bus request to the arbiter even though the transfer request is asserted This operation prevents the DMAC from blocking the bus This transfer gap can be used to update register settings e g disable interruption setting to the DMAC during DMA transfers Transfer request External DREQ and peripheral IDREQ requests are permissible in demand transfer mode however software requests are pro...

Page 289: ... signals indicate that the DMAC is receiving a demand transfer request 8 DEOP IDEOP Basically DEOP IDEOP are asserted for 1 AHB clock HCLK cycle when DMAC ends DMA transfer properly or abnormally Abnormal DMA transfer includes following cases Forced termination by DSTP IDSTP Forced termination by setting 1 b0 to DMACA EB Receiving error response from source destination DSTP IDSTP are used to forci...

Page 290: ...V1 64 DACK DREQ DEOP DSTP HCLK HBUSREQM HDMAC HGRANTM HDMAC HMASTER Control HREADY IDLE READ HRESP NOSEQ or SEQ READ or WRITE HDMAC OK Other mster Other mster NOSEQ or SEQ READ or WRITE Figure 15 6 Example of DEOP IDEOP exception operation ...

Page 291: ...LK HADDR HWRITE Control External trigger HWDATA HRDATA HBUSREQ HGRANT HREADY HRESP HMASTER CPU HDMAC CPU OK SA DA HTRANS N N I Data Data DMACA 19 16 0x2 BC 0x1 0x0 DMACA 15 0 0x0 TC 0x0 HDMAC SA DA N N I HDMAC SA DA N N I Data Data Data Data Transfer gap Transfer gap Figure 15 7 Demand transfer for BC 0x0 should be 0 and TC 0x2 ...

Page 292: ...ACA BT Beat transfer type HBURST DMACA MS mode select Block Burst Demand 4 b0000 Normal Single OK OK OK 4 b1000 Single Single OK OK OK 4 b1001 INCR INCR OK OK NG 4 b1010 WRAP4 WRAP4 OK OK NG 4 b1011 INCR4 INCR4 OK OK NG 4 b1100 WRAP8 WRAP8 OK OK NG 4 b1101 INCR8 INCR8 OK OK NG 4 b1110 WRAP16 WRAP16 OK OK NG 4 b1111 INCR16 INCR16 OK OK NG In demand transfer mode increment lap burst INCR and WRAP ar...

Page 293: ...IFO In the case of INCR4 DMACA BT 4 b1011 the DMAC performs 4 sequential source accesses Output data from the source is stored in the DMAC s FIFO then the data is sequentially driven to the destination HCLK HADDR HWRITE Control HWDATA HRDATA HBUSREQ HGRANT HREADY HRESP HMASTER CPU HDMAC CPU OK SA SA SA SA DA DA HTRANS N S S S S I N D4 D1 D1 DMACA 19 16 BC 0x0 DMACA 15 0 TC DA DA S S INCR4 INCR4 D2...

Page 294: ...nnel ch0 can be selected by the priority controller to start a transfer For example the active channel ch0 temporarily loses the bus during the transfer gap The second lowest numbered channel ch1 is then granted bus access When ch1 loses the bus control during the transfer gap it is given to ch0 again As a result these 2 channels are able to preferentially acquire bus usage in fixed priority mode ...

Page 295: ...e transfer operation In rotate priority mode all channels are able to acquire the bus in turn For example the active channel ch0 temporarily loses the bus during the transfer gap Access is then granted to the second lowest numbered channel ch1 When ch1 loses the bus access during the transfer gap it is granted to the third lowest numbered channel ch2 Figure 15 10 shows the defined channel ordering...

Page 296: ...response during INCR4 DMA transfer HCLK HADDR HWRITE Control HWDATA HRDATA HBUSREQ HGRANT HREADY HRESP HMASTER CPU HDMAC CPU OK SA SA SA SA DA DA HTRANS N S S S S I N D4 D1 D1 DMACA 19 16 BC 0x0 DMACA 15 0 TC DA DA S S INCR4 INCR4 D2 D3 D2 D3 D4 0x0 RETRY OK HDMAC DA N I D4 INCR Figure 15 11 Increment Lap beat transfer example of INCR4 block transfer When DMAC negates bus temporarily the channel r...

Page 297: ...receives an error reply from an AHB slave during DMA transfer it negates the bus request and immediately stops the transfer even though it has not been completed In this case neither the Block Transfer count register nor the Source Destination address registers are updated ...

Page 298: ...000 Destination address is set Transfer mode transfer data width and completion interrupt are set In this example block transfer mode MS 1 0 0H is set as transfer mode Burst transfer mode is able to be set by MS 1 0 1H DMA channel transfer control software trigger and number of block and transfer are set 5 Set DMA configuration A register DMACA0 0xA00F_000F Start DMA transfer Remark Setting order ...

Page 299: ...igger and number of block and transfer are set 5 Set DMA configuration A register DMACA0 0x9000_000A Start DMA transfer Remark Setting order of step 1 5 is arbitrary however the last setting should be step 1 or 5 Note DMA configuration register DMACR should be set by byte writes 15 8 2 DMA start in all channels in demand transfer mode All channels are able to start simultaneously by setting the DM...

Page 300: ...nd that forwarding can be done efficiently These settings can be specified by the CMD byte allowing a highly flexible solution that abstracts the type of host CPU in use and the access objects Supports communication to a host CPU with an SPI interface The length of the SPI interface packets is variable to permit the use of variable length addresses and data accesses Supports writes reads to the in...

Page 301: ...e data byte length can be arbitrarily set in a range of 1 to 16 bytes This module provides a function to notify the host CPU with the result of write processing It is necessary to send a dummy write CMD after a normal write CMD The host CPU serial clock is maintained by sending dummy write CMDs The result of write processing is sent with this clock The basic format of a write access is shown below...

Page 302: ...tes 0 0 1 1 0 1 0 2 0 1 1 4 1 0 0 8 1 0 1 12 1 1 0 16 16 1 1 1 AHB HSIZE no access Byte Half word 1 word 2 word 3 word 4 word 4 word AHB HBURST no access SINGLE SINGLE SINGLE INCR INCR INCR4 INCR4 R W Specifies read or write 1 is a write STATUS byte The write status is shown by the TxRDY bit of the STATUS byte When write processing is completed and the next transmission is possible 1 is shown in t...

Page 303: ...myWrite set CMD_ DBL 2 1 0 0 0 LightGDC sends ReadS ts0 until ReadS ts becomes ReadS ts1 Read complete ABL ABL DBL DBL DBL R W C NT C NT ABL 1 0 Address Byte Length 1 4 Byte DBL 2 0 Data Byte Length 1 16Byte R W R ead or Write select C NT 1 0 C ommand for control by HOS T 10 R S T other not R S T TxR DY R xR DY S E R R R x R DY Tx R DY 1 S E R R 1 1 1 1 0 WriteS ts0 1 WriteS ts1 0 R eadS ts0 1 R e...

Page 304: ...16 5 MB86R02 Jade D Hardware Manual V1 64 The flow of a read action is shown below Figure 16 5 Read process flow ...

Page 305: ... from internal module INT Status byte HOST DO Rx RDY Tx RDY 1 SERR 1 1 1 1 1 1 0 1 0 1 Initial Disable Figure 16 6 Interrupt When an error response status has been sent to the host CPU the transaction is completed If the CCNT interrupt setting is enabled an interrupt is generated 16 3 4 Reset Request A software reset of MB86R02 can be executed on request by the host CPU If the normal operation of ...

Page 306: ...rams 16 4 1 1 SPI protocol stack The SPI communication protocol stack is shown below CCNT CCNT interrupt DATA SPI SPI interface AHB Master AHB Modules Host CPU BUS SPI CPU BUS Modules interrupt Controller Handshaking RxRDY TxRDY DATA RST Handshaking RxRDY TxRDY RST Figure 16 8 SPI communication protocol stack ...

Page 307: ...ue to an initialization by the MB86R02 s watchdog timer WDT or by initialization via a RST CMD In this case the arrangement of the data bytes would be mistakenly interpreted It is therefore necessary to use a reset frame when initializing when the HOSTIF module is communicating HOST XCS Whenthe SCLK never reaches the period whenthe XCS signal is active First byte CMD byte Condition of XCS width Ho...

Page 308: ...d byte ABL 0 byte Last byte CMD byte HRESET or Reset Fram e Last byte ST DB byte Figure 16 11 Non continuous data bytes with non continuous HOST XCS 16 4 2 3 2 Non continuous data bytes with continuous HOST XCS HOST DO HOST DI HOST XCS HOST SCK First byte CMD byte second byte ABL 0 byte Last byte CMD byte HRESET or Reset Frame Last byte ST DB byte Figure 16 12 Non continuous data bytes with contin...

Page 309: ...therefore it is not necessary to repeat the address byte with every access This implements a very effective forwarding mechanism an example of which is shown below swap is not set ABL 4byte CMD DBL 16byte ADD07 00 ADD15 08 ADD23 16 ADD31 24 DT07 00 DT15 08 DT23 16 DT31 24 AB 0 AB 1 AB 2 AB 3 DB 0 DB 1 DB 2 DB 3 ABL 1byte CMD ADD07 00 DT07 00 DT15 08 DT23 16 DT31 24 AB 0 DB 0 DB 1 DB 2 DB 3 ABL 1by...

Page 310: ...B86R02 devices does not have a CRC error correction function The normal operation of the MB86R02 can not be guaranteed if the CLK signal exceeds specified boundaries DmyWrite WriteS ts 0 WriteS ts 1 WriteS ts 0 WriteS ts 0 HOS T DO AD D 07 00 AD D 15 08 AD D 23 16 AD D 31 24 D T07 00 D T15 08 D T23 16 D T31 24 C MD AB 0 AB 1 AB 2 AB 3 DB 0 DB 1 DB 2 DB 3 HOS T HOS T HOS T DI C MD Next Read or Writ...

Page 311: ...HOST XCS HOST DI STATUS Dum my Write Write Rx RDY Tx RDY SERR ABL1 ABL0 DBL2 DBL1 DBL0 R W CNT1 CNT0 Write WriteSts1 x 0 0 0 0 1 0 x 0 1 1 0 1 1 1 1 Figure 16 17 Dummy Write R W bit WRITE 16 1 1 1 2 When the first CMD is a dummy Read R W bit Read RxRDY is sent back for dummy READ CMD Refer to Figure Error No text of specified style in document ReadSts1 HOST DO CMD HOST SCK HOST XCS HOST DI STATUS ...

Page 312: ... Idol Idol don t send Deadlock detection Soft TIMER WDT detect 1 detect Deadlock Idol or Deadlock Idol or Deadlock detect detect waiting resp Deadlock send wait Sts0 detect detect Cause of Deadlock in Slave in AHB BUS in HOST IF or IF waiting resp waiting resp send wait Sts0 detect detect detect not detect 2 not detect 2 not detect 2 Deadlock point waiting resp Deadlock send wait Sts0 Deadlock Ido...

Page 313: ...the software timer ReadSts0 STATUS ReadSts0 STATUS ReadSts0 STATUS ReadSts0 STATUS ReadSts0 STATUS ReadSts0 STATUS ReadSts0 STATUS DmyWrite CMD DmyWrite CMD ReadSts0 STATUS ReadSts0 STATUS RST req CMD ReadSts0 STATUS STA Start Software TIMER of HOST Reboot Indigo ABL1 ABL0 DBL2 DBL1 DBL0 R W CNT1 CNT0 t Beginning of data transfer Reset is demanded Time out e g 0 5sec The software timer detects the...

Page 314: ...ev 1 0 The downstream link provides the following Bandwidth Modes Full Bandwidth Mode 1000 Mbit s Half Bandwidth Mode 500 Mbit s Low bandwidth Mode 1 125 Mbit s Low bandwidth Mode 2 250 Mbit s One single video channel Further features of the APIX PHY module are Establishment and maintenance of serial frame alignment Framing deframing serial frames Line coding and DC balancing Serialization deseria...

Page 315: ...e band channel only Therefore it is not possible to transfer pixel data in both Low Bandwidth modes Please note that the application software can not use the PLL_GOOD register to correctly evaluate the status of the APIX PLL if separate ECLK and XTAL clock sources are used for the core and APIX units respectively The internal signal pll_good which sets the PLL_GOOD register is not cleared if the e...

Page 316: ...nit Ch1 Ch1 APIX PHY Ch0 RX TX APIX Ashell Ch0 RX TX CAP Unit AHB Bus Pixel Pipeline APIX Pins Ch0 Sideband Control data Video data Video data DISP Unit Pixel Pipeline APIX Reg IF APIX Pins Ch1 APIX SBGPIO Figure 17 1 Block diagram of APIX PHY RX and APIX Ashell RX in the System ...

Page 317: ...r Bit number shows bit position of the register Field name Field name shows bit name of the register R W R W shows the read write attribute of each bit field R Read W Write W1C Writing a value of 1 clears the register Reset value Reset value indicates the value of each bit field immediately after reset 0 Initial value is 0 1 Initial value is 1 X Undefined Unused register fields are marked with a s...

Page 318: ... 0 Base address 3CH R0STS1 Channel 0 RX status register 1 Base address 40H CH1CFG Channel 1 Config Base address 44H T1CFG0 Channel 1 TX APIX configuration byte 1 4 Base address 48H T1CFG1 Channel 1 TX APIX configuration byte 5 8 Base address 4CH T1CFG2 Channel 1 TX APIX configuration byte 9 11 Base address 50H T1CFG3 Channel 1 TX APIX SHELL configuration byte1 4 Base address 54H T1CFG4 Channel 1 T...

Page 319: ...one phase Bit 9 CH0SDIN_Invert 1 Invert data on SDIN pin PCB optimization Bit 8 CH0SDOUT_Invert 1 Invert data on SDOUT pin PCB optimization Bit 6 3 CH0UpNomSwing Transmit swing binary coded 1 LSB 0 53mA 0000 min 4mA 0001 4 53mA 1111 max 12mA Bit 2 Reserved Do not modify Bit 1 0 Reserved Do not modify T0CFG0 Register address BaseAddress 4H Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ...

Page 320: ...3 apix config byte see section 17 4 Bit 15 8 T0_config_byte_shell_2 apix config byte see section 17 4 Bit 7 0 T0_config_byte_shell_1 none T0CFG4 Register address BaseAddress 14H Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field name T0_DeEmph T0_CFG4_reserved0 R W RW RWS Reset value 0H 0H Channel 0 TX APIX configuration Bit 17 16 T0_DeEmph Trans...

Page 321: ...t become TA aligned CONNECTED is low If the local APIX PHY is not used PHYUPRDY is forced to 1 tx_up_ready Bit 0 T0PLLGOOD pll_good is the same for all Tx Rx channels T0STS1 Register address BaseAddress 20H Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field name Reserved T0INSYNC T0PLLBAD R W R R R Reset value 0H 0H 0H Channel 0 TX status registe...

Page 322: ...on 17 4 Bit 15 8 R0_config_byte_shell_2 apix config byte see section 17 4 Bit 7 0 R0_config_byte_shell_1 none R0CTRL Register address BaseAddress 34H Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field name Reserved R0CFGEN Reserved R W RWS RW RW Reset value 0H 1H 0H Channel 0 RX control Bit 31 24 Reserved Do not modify Bit 2 R0CFGEN 0 A Shell and...

Page 323: ...d_cnt CH1CFG Register address BaseAddress 40H Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field name CH1ENDwnP hy CH1ENUpPhy CH1SDINCD R_Bw CH1SDINWin dow CH1SDIN_Inv ert CH1SDOUT_I nvert CH1UpNomS wing Reserved Reserved R W RW RW RW RW RW RW RW RW RW Reset value 0H 0H 0H 6H 0H 0H FH 0H 1H Channel 1 Config Bit 31 CH1ENDwnPhy Enable Downstream PH...

Page 324: ...ix config byte see section 17 4 Bit 15 8 T1_config_byte_6 apix config byte see section 17 4 Bit 7 0 T1_config_byte_5 none T1CFG2 Register address BaseAddress 4CH Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field name Reserved T1_config_byte_11 T1_config_byte_10 T1_config_byte_9 R W RWS RW RW RW Reset value 0H 40H 2H 2H channel 1 TX APIX configur...

Page 325: ... EnRstToPhy is enabled is hold in reset Changes at configurations bytes config_byte_ are allowed only when CFGEN or RSTRT are asserted Bit 1 Reserved Do not modify T1STS0 Register address BaseAddress 5CH Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserve...

Page 326: ... see section 17 4 Bit 7 0 R1_config_byte_1 none R1CFG1 Register address BaseAddress 68H Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field name Reserved R1_config_byte_7 R1_config_byte_6 R1_config_byte_5 R W RWS RW RW RW Reset value 0H 93H C0H 3FH channel 1 RX APIX configuration byte 5 7 Bit 31 24 Reserved Do not modify Bit 23 16 R1_config_byte_7...

Page 327: ... R Reset value 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H Channel 1 RX status register 0 Bit 31 24 Reserved Do not modify Bit 17 Reserved Do not modify Bit 10 R1PXALIGND rx_pix_aligned 1 Pixel link operational Bit 9 Reserved Do not modify Bit 8 Reserved Do not modify Bit 7 Reserved Do not modify Bit 6 Reserved Do not modify Bit 5 Reserved Do not modify Bit 4 Reserved Do not modify Bit 3 Reserved Do no...

Page 328: ...Bit 31 16 MiscCfg reserved Bit 11 8 Atst_sel Select use of ATST pad 0 not used 1 Vco control voltge 2 Bandgap voltage 3 Reference current Bit 4 Mask_pll_good Masks pllGood for reset in digital 0 pll_good reset_n signals used to reset digital 1 only reset_n signal is used to reset digital Bit 3 Reserved Do not modify APPLLCFG Register address BaseAddress 10CH Bit number 31 30 29 28 27 26 25 24 23 2...

Page 329: ...0 83 MBit s 11 31 25 MBit s not applicable Note upstream bandwidth setting has to match related transmitter device configuration 6 0 cfg_up_clk_divider 0 5 1 reserved reserved 4 1 reserved 3 1 reserved 2 1 reserved 1 0 reserved 0 1 cfg_sbup_smode APIX PHY relation of upstream sideband data to core clock of APIX PHY 0 asynchronous 1 synchronous Table 17 2 RX config_byte_1 1 If a setup with the exte...

Page 330: ..._ctrl_piggyback 1 APIX PHY transmission of pixel control signals px_ctrl 2 0 used for HSYNC VSYNC DE 00 never 01 unused 10 with even pixels only 11 with every pixel Note pixel control signals setting has to match related transmitter device configuration Note to achieve maximum pixel link net bandwidth setting 10 is necessary see APIX standard 4 1 cfg_px_out_ctrl_piggyback 0 3 1 Reserved do not cha...

Page 331: ...2 1 reserved do not change 1 1 reserved do not change 0 0 reserved do not change Table 17 4 RX config_byte_3 config_byte_4 Bit init ial Name Description 7 0 reserved do not change 6 0 reserved do not change 5 0 reserved do not change 4 0 reserved do not change 3 0 reserved do not change 2 0 reserved do not change 1 0 reserved do not change 0 0 reserved do not change Table 17 5 RX config_byte_4 ...

Page 332: ...anual V1 64 config_byte_5 Bit init ial Name Description 7 0 reserved reserved 6 0 reserved 5 1 reserved 4 1 reserved 3 1 reserved reserved 2 1 reserved reserved 1 1 reserved reserved 0 1 reserved reserved Table 17 6 RX config_byte_5 ...

Page 333: ...de 0 5 0 cfg_ddown_enable APIX PHY AShell configure downstream data path 0 disable data mode enable pixel stream mode 1 enable data mode disable pixel stream mode Note for proper operation of data mode the following settings are also mandatory cfg_pxdata_width 1 0 00 cfg_px_out_ctrl_piggyback 1 0 00 4 0 reserved do not change 3 0 reserved do not change 2 0 reserved do not change 1 0 reserved do no...

Page 334: ... do not change 6 0 reserved 5 0 reserved 4 1 reserved 3 0 reserved do not change 2 0 reserved do not change 1 1 cfg_clk_core1_enable APIX PHY digital 1 enable core clock of APIX PHY 0 disable 0 1 cfg_clk_core2_enable APIX PHY digital 1 enable core clock of AShell 0 disable Table 17 8 RX config_byte_7 ...

Page 335: ... 0 cfg_sbup_daclk_clength 6 1 0 cfg_sbup_daclk_clength 5 0 0 cfg_sbup_daclk_clength 4 Table 17 9 RX config_byte_shell1 cfg_downBWMode 1 0 cfg_up_clk_divider 1 0 cfg_sbup_daclk_clength 10 0 supported minimum value 11 01 14 11 10 20 11 11 26 10 00 00 8 10 00 01 14 10 00 10 20 Table 17 10 Rule for minimum cfg_sbup_daclk_clength paramter cfg_mode_sb cfg_downBWMode C cfg_sbup_daclk_clength 10 0 resulti...

Page 336: ...k_clength 1 4 0 cfg_sbup_daclk_clength 0 3 1 cfg_sbup_dwidth AShell enable sbup ports 1 sbup_data 1 0 0 sbup_data 0 2 0 cfg_sbup_daclk 1 AShell generate sbup clock and transmit as sbup_data 1 11 disable 10 with use of internal counter asynchronous to core_clk of APIX PHY 01 reserved 00 disable 1 0 cfg_sbup_daclk 0 0 1 cfg_sbdown_dwidth AShell enable sbdown ports 1 sbdown_data 1 0 0 sbdown_data 0 T...

Page 337: ... disable 4 0 cfg_mode_sb AShell selects between two different sideband transmission modes 0 mode 0 toggle mode see Figure 17 28 1 mode 1 see Figure 17 29 3 1 cfg_crc_timeout_value 3 AShell CRC timeout error is generated after N consecutively received and corrupted transitions CRC mismatch N factor1 factor2 factor1 cfg_crc_timeout_value 3 2 factor2 cfg_crc_timeout_value 1 0 factor 1 factor 2 00 1 0...

Page 338: ...acknowledge protocol supported size 1 12 6 0 cfg_window_size 2 5 1 cfg_window_size 1 4 0 cfg_window_size 0 3 0 cfg_arq_off AShell disable automatic repetition request ARQ 1 ARQ disabled 0 ARQ enabled 2 0 cfg_suppress_ita AShell outbound idle transactions are not sent 1 enable 0 disable 1 0 reserved 0 0 reserved Table 17 14 RX config_byte_shell4 ...

Page 339: ... init ial Name Description 7 1 reserved do not change 6 1 reserved do not change 5 1 reserved do not change 4 1 reserved do not change 3 0 reserved do not change 2 0 reserved do not change 1 0 reserved do not change 0 0 reserved do not change Table 17 15 TX config_byte_1 ...

Page 340: ...s only 11 with every pixel 2 1 cfg_px_in_ctrl_piggyback 0 1 1 cfg_pxdata_width 1 APIX PHY Soft IP bit width of pixel data 00 10 bits 01 12 bits 10 18 bits 11 24 bits 0 0 cfg_pxdata_width 0 Table 17 16 TX config_byte_2 The maximum pixel clock frequencies listed in Table 17 1 are achievable only if pixel controls are transmitted with even pixels cfg_px_in_ctrl_piggyback 10 pixel data bit width maxim...

Page 341: ...it s mode 0010 optimum sampling point when operating in 41 67 Mbit s or 31 25 Mbit s mode 0100 optimum sampling point when operating in 20 83 Mbit s mode 2 0 cfg_upSmpOfst 2 1 0 cfg_upSmpOfst 1 0 0 cfg_upSmpOfst 0 Table 17 17 TX config_byte_3 config_byte_4 Bit init ial Name Description 7 1 reserved do not change 6 0 reserved do not change 5 0 reserved do not change 4 1 reserved do not change 3 0 r...

Page 342: ...IP relation of downstream sideband data to core clock of APIX PHY 0 asynchronous sb data are 2 stage registered internal have to be used with external AShell 1 synchronous have to be used with internal AShell 5 1 cfg_clk_core1_enable APIX PHY Soft IP 1 enable core clock of APIX PHY 0 disable 4 0 cfg_clk_core2_enable APIX PHY Soft IP 1 enable core clock of Ashell 0 disable 3 0 reserved do not chang...

Page 343: ...de D Hardware Manual V1 64 5 1 reserved do not change 4 1 reserved do not change 3 0 reserved do not change 2 0 reserved do not change 1 1 reserved do not change 0 1 reserved do not change Table 17 19 TX config_byte_6 ...

Page 344: ... s pulse pattern 9 required when operating in Full and Half Bandwidth Mode 18 required when operating in Low Bandwidth Mode 2 APIX PHY core_clk 62 5 MHz 36 required when operating in Low Bandwidth Mode 1 APIX PHY core_clk 62 5 MHz 36 required when operating in Low Bandwidth Mode 2 APIX PHY core_clk 125 MHz 72 required when operating in Low Bandwidth Mode 1 APIX PHY core_clk 125 MHz 6 0 cfg_trigger...

Page 345: ...e_length 2 2 0 cfg_trigger_active_length 1 1 1 cfg_trigger_active_length 0 0 0 reserved do not change Table 17 4 TX config_byte_9 config_byte_10 Bit init ial Name Description 7 0 cfg_trigger_offset 6 APIX PHY Soft IP configure start position of signal sbdown_trigger multiples of core clk cycle relative to strobe position 0 0 cycles strobe 1 1 cycle request 1 2 cycles 71 71 cycles 6 0 cfg_trigger_o...

Page 346: ...igure high pulse width of signal sbup_valid multiples of core clk cycle 11 4 cycles 10 3 cycles 01 2 cycles 00 1 cycle 6 1 cfg_sbup_valid_active_length 0 5 0 reserved do not change 4 0 reserved do not change 3 0 reserved do not change 2 0 reserved do not change 1 0 reserved do not change 0 0 reserved do not change Table 17 21 TX config_byte_11 ...

Page 347: ...ell configures cycle time of sbdown clock multiples of Ashell core clock when sbdown_data are asynchronous sbdown_data 1 is used as sbdown clock or cfg_mode_sb is enabled mode1 11 recommended minimum no low bandwidth mode AShell and APIX PHY operate at same core clock frequency 20 recommended minimum low bandwidth mode 2 AShell and APIX PHY operate at 62 5 MHz 5 1 cfg_sbdown_daclk_clength 5 4 0 cf...

Page 348: ...minimum value 11 01 14 11 10 20 11 11 26 10 00 00 8 10 00 01 14 10 00 10 20 Table 17 23 Rule for minimum cfg_sbup_daclk_clength paramter cfg_mode_sb cfg_downBWMode C cfg_sbup_daclk_clength 10 0 resulting data rate Mbit s 0 11 125 106 C 0 10 00 62 5 106 C 1 11 125 106 2 C 1 10 00 62 5 106 2 C Table 17 24 Formula for resulting uplink datarate ...

Page 349: ...le 10 with use of internal counter asynchronous to core_clk of APIX PHY 01 with use of sbdown_trigger synchronous to core_clk of APIX PHY 00 disable 3 0 cfg_sbdown_daclk 0 2 0 cfg_ephy AShell connect internal Ashell to external APIX PHY through GPIO interface 1 enable 0 disable 1 1 cfg_eshell AShell connect internal APIX PHY to external AShell through GPIO interface 1 enable 0 disable 0 0 cfg_mode...

Page 350: ...t base x multiplier example 1011 16 10 160 multiplier 3 2 base 1 0 00 1 00 2 01 4 01 4 10 16 10 6 11 128 11 10 6 0 cfg_crc_timeout_value 2 5 0 cfg_crc_timeout_value 1 4 1 cfg_crc_timeout_value 0 3 1 cfg_window_size 3 AShell defines the window size of the acknowledge protocol supported size 1 12 2 0 cfg_window_size 2 1 1 cfg_window_size 1 0 0 cfg_window_size 0 Table 17 26 TX config_byte_shell3 ...

Page 351: ...idle transactions are not sent 1 enable 0 disable 5 0 reserved 4 0 reserved 3 0 reserved 2 0 cfg_sbdown_daclk_clength 9 upper bits of cfg_sbdown_daclk_clength in config_byte_shell_1 1 0 cfg_sbdown_daclk_clength 8 0 0 cfg_sbdown_daclk_clength 7 Table 17 27 TX config_byte_shell4 17 5GPIO Interface Timing of Sideband Uplink and Downlink Figure 17 28 Mode 0 dual edge transmission Figure 17 29 Mode 1 s...

Page 352: ...hell Tn set CHnCFG ENUpPHY 1 set CHnCFG ENDwnPHY 1 Enable upstream downstream PHY deactivate resets Set APPLLCFG PhyPllReset 0 PLL reset deactivate Set COMPHYCFG SwRstToPHY APIX PHY reset deactivate set TnCTRL CFGEN 1 set TnCFG0 xx set TnCFG1 xx set TnCFG2 xx set TnCTRL CFGEN 0 read TnSTS0 check for TnPHYUPREADY 1 TnPLLGOOD 1 provide valid pixeldata RGB HS VS DE read Indigo RH ASStatus check for r...

Page 353: ...n_SB_0 in TDAn0 out Sideband GPIO Data bit 0 down APIXn_SB_1 in TDAn1 out Sideband GPIO Data bit 1 APIXn_SB_2 out TCKIn in Sideband Clock APIXn_SB_3 out RDAn0 in Sideband GPIO Data bit 0 up APIXn_SB_4 out RDAn1 in Sideband GPIO Data bit 1 APIXn_SB_5 out RCKn in Sideband Clock Table 17 6 Use Case 1 n channel number 0 1 17 6 1 1 1 Jade D configuration Table 17 7 Jade D APIX TX configuration vectors ...

Page 354: ...nfiguration vectors for use case 1 MCU467S configuration config_byte_1 00h config_byte_2 30h config_byte_3 00h config_byte_4 90h config_byte_5 50h config_byte_6 00h config_byte_7 00h config_byte_8 48h config_byte_9 02h config_byte_10 02h config_byte_11 40h config_byte_shell_1 26h config_byte_shell_2 A4h config_byte_shell_3 9Ah config_byte_shell_4 00h ANALOG PARAMETERS are subject to change 17 6 1 ...

Page 355: ... 17 6 1 2 Use case 2 Feedthrough of 1bit sideband data MCU467S Ashell Jade D APIX PHY TX Indigo APIX PHY RX Ashell 1bit Sideband Datawidth Figure 17 31 Use Case 2 Jade D MCU467S pin name direction pin name direction function APIXn_SB_0 in TDAn0 out Sideband GPIO Data bit 0 down APIXn_SB_1 unused APIXn_SB_2 out TCKIn in Sideband Clock APIXn_SB_3 out RDAn0 in Sideband GPIO Data bit 0 up APIXn_SB_4 u...

Page 356: ...6h config_byte_shell_2 02h config_byte_shell_3 9Ah config_byte_shell_4 00h Configuration Vector config_byte_shell_2 Bit Default Name Description 7 0 cfg_sbup_dwidth AShell enable sbup ports 1 sbup_data 1 0 0 sbup_data 0 5 0 cfg_sbdown_dwidth AShell enable sbdown ports 1 sbdown_data 1 0 0 sbdown_data 0 All other parameters are default reset values 17 6 1 2 2 MB91F467SA configuration Table 17 12 MB9...

Page 357: ...yte_shell_1 00h config_byte_shell_2 E0h config_byte_shell_3 09h config_byte_shell_4 A0h ANALOG PARAMETERS are subject to change Table 17 13 Indigo Configuration 17 6 2 Application Notes for PCB Designers Full documentation of the configuration of pins related to the APIX unit is not yet available The following information describes APIX related pins and their configuration for PCB designers OSC_MO...

Page 358: ... has been validated and real life values measured it is not possible to make a fixed recommendation for a specific application However until then setting 11 makes the most sense best clock characteristics but higher current consumption OSC_FILTER Sets the characteristics of an internal low pass post oscillator filter This filter is integrated in order to improve the robustness of the internal circ...

Page 359: ...d video images on the same screen Geometry Engine The Geometry Engine executes geometry processing and is basically compatible with Coral PA Display lists created for Coral series MB86293 MB86296 GDCs can be drawn When intensive geometric operations processing such as coordinate conversions or clipping are performed by this GDC the workload of a CPU can be dramatically reduced 2D and 3D Drawing Th...

Page 360: ...od Double buffer method in which drawing window and display window is switched in units of 1 frame enables the smooth animation Flipping switching of display window area is performed in synchronization with the vertical blanking period using program Scroll method Independent setting of drawing and display windows and their starting positions makes smooth scrolling possible Display colors Supports ...

Page 361: ...ndow mode Up to six screens L0 to 5 can be displayed overlaid The overlay sequence of the L0 to L5 layers can be changed arbitrarily The overlay position for the hardware cursors is above below the L0 layer The transparent mode or the blend mode can be selected for overlay The L5 layer can be used as the blend coefficient plane 8 bits pixel Window display can be performed for all layers Four palet...

Page 362: ...drawing mode and primitive type and executes processing for the final drawing Primitives Point line line strip independent triangle triangle strip triangle fan and arbitrary polygon are supported MVP Transformation MVP Transformation A 4 4 transformation matrix enables the transformation of a 3D model view projection Two dimensional affine transformation is also possible Clipping Clipping stops th...

Page 363: ...sed to draw polygons 2D Primitives Primitive type Description Point Plots a point Line Draws a line Bold line strip provisional name Draws a continuous bold line This primitive is used when interpolating the joint of a bold line Triangle Draws a triangle High speed 2D Line Draws lines Compared to Line this reduces the host CPU processing load Arbitrary polygon Draws arbitrary closed polygon contai...

Page 364: ...forms BLT without drawing pixel consistent with the transparent color Alpha blending The alpha map and source in the memory is subjected to alpha blending and then copied to the destination Pattern Text drawing This function draws a binary pattern text in a specified color Pattern Text Drawing Attributes Attribute Description Enlarge Vertically 2 Horizontally 2 Vertically and Horizontally 2 Shrink...

Page 365: ...raws arbitrary closed polygon containing concave shapes consisting of vertexes 3D Drawing attributes Texture mapping with bi linear filtering automatic perspective correction and Gouraud shading provides high quality realistic 3D drawing A built in texture mapping unit performs fast pixel calculations This unit also delivers color blending between the shading color and texture color Hidden plane m...

Page 366: ...g points Supports vertical broken line patterns Interpolation of bold line joints supports the following modes 1 Broken line pattern reference address fix mode The same broken line pattern is continuously referenced during the period of some pixels starting from the joint and the starting point for the next line 2 No interpolation Supports width equalization of bold lines Supports bold line edging...

Page 367: ...d at texture mapping When the most significant bit of each texture cell is 1 drawing or transparency can be set When the most significant bit of each texture cell is 0 non drawing can be set Alpha Blending Type Description Drawing Transparent ratio set in particular register While one primitive polygon pattern etc being drawn registered transparent ratio applied A transparent coefficient set for e...

Page 368: ...Filtering Point sample Bi linear filter Coordinates correction Linear Perspective Blend Decal Modulate Stencil Alpha blend Normal Stencil Stencil alpha Wrap Repeat Cramp Border 18 3 7 Others Top left rule non applicable mode In addition to the top left rule applicable mode in which the triangle borders are compatible with Coral PA the top left rule non applicable mode can be used Caution Use persp...

Page 369: ...MB86296 Coral PA as follows the register area and the VRAM area are separated in the MB86R02 Jade D memory map Two VRAM segment areas are mapped for MB86R02 Jade D GDC Registers 1 MB86296 Coral PA 64MB F1FF_FFFFH F1FC_0000H Registers 4800_0000H 4000_0000H 128MB VRAM area Register area 2 MB86R02 Reserved 4400_0000H Segment 1 64MB Segment 0 64MB ...

Page 370: ...yers Z Buffer A Z buffer is required for the elimination of hidden surfaces In 16 bit modes 2 bytes are required per pixel and in 8 bits mode 1 byte is required per pixel This area must be cleared before drawing Polygon Drawing Flag Buffer This area is used for polygon drawing It requires 1 bit of the memory area per pixel and 1 x axis line area both in front and behind it This area must be cleare...

Page 371: ...1 0 A R G B Indirect Color 8 bits pixel This data format is a color index code for the lookup table palette 7 6 5 4 3 2 1 0 Color Code Z Value It is possible to use 8 bits or 16 bits for a Z value The data format is unsigned integer 1 16 bits mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unsigned Integer 2 8 bits mode 7 6 5 4 3 2 1 0 Unsigned Integer Polygon Drawing Flag This data format is 1 bit per...

Page 372: ... table palette 7 6 5 4 3 2 1 0 Color Code Cursor Pattern This data format is a color index code into the lookup table palette 7 6 5 4 3 2 1 0 Color Code Video Capture data This data format is Y Cb Cr 4 2 2 and 32 bits per 2 pixels 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Y0 Cb 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Y1 Cr Direct Color 32 bits pixel This data format describes an RGB value with...

Page 373: ... be logically connected to the bottom and right edges respectively To avoid artefacts by drawing directly on the display drawing data can be transferred to the graphics memory in the blanking time period 18 5 2 Double Buffer Two drawing frames are set up While one frame is being displayed drawing is done to the other frame Flicker less animation can be performed by switching back and forth between...

Page 374: ...hronous PWM shares GVi output This PWM is based on a 12 bit counter and is synchnonous with the video clock The Hsync and Vsync signala can be used to reset the count 4 Two independent capture inputs Both ports accept ITU 656 and ITU 601 format in parallel Only one port accepts the RGB666 format video timing controller video data processor video data processor video timing controller DCLKO1 HSYNC1...

Page 375: ...W WH 1 L2 ML L2WX L2WY 0 0 L2WW L2WH 1 HDB 1 VDP 1 L3 MR L3WX L3WY HDB 0 L3WW L3WH 1 HDP HDB VDP 1 L4 BL L4WX L4WY 0 0 L4WW L4WH 1 HDB 1 VDP 1 L5 BR L5WX L5WY HDB 0 L5WW L5WH 1 HDP HDB VDP 1 C W ML MR BL and BR above refer to layers of previous products Window mode or compatibility mode can be selected for each layer It is possible to use new functions via minor program changes by allowing the coe...

Page 376: ...verlaid before blend operation The L1 layer corresponds to the W layer for previous products To implement backward compatibility with previous products the L1 layer and lower layers are overlaid before blend operation The L2 to L5 layers have two paths in one path these layers are input to the blender separately and in the other these layers and the L1 layer are overlaid and then are input to the ...

Page 377: ...lways performed assuming that transparent color is not used In the blend mode the blend ratio r defined for each layer is specified using 8 bit tolerance and the following operation is performed Dview Dnew r Dlower 1 r Blending is enabled for each layer by mode setting and a specific bit of the pixel is set to 1 For 8 bits pixel the MSB of RAM data enables blending for 16 bits pixel the MSB of dat...

Page 378: ...ntal Total Pixels HSP Horizontal Synchronize pulse Position HSW Horizontal Synchronize pulse Width HDP Horizontal Display Period HDB Horizontal Display Boundary VTR Vertical Total Raster VSP Vertical Synchronize pulse Position VSW Vertical Synchronize pulse Width VDP Vertical Display Period LnWX Layer n Window position X LnWY Layer n Window position Y LnWW Layer n Window Width LnWH Layer n Window ...

Page 379: ...splay Position Parameters OA Origin Address Origin address of logical graphics space Memory address of top left edge pixel in logical frame origin W Stride Width of logical graphics space Defined in 64 byte unit H Height Height of logical graphics space Total raster pixel count of field DA Display Address Display origin address Top left position address of display frame origin DX DY Display Positi...

Page 380: ...hown below Wrap Around of Display Frame The expression of the X and Y coordinates in the frame and their corresponding linear addresses in bytes is shown below A x y x bpp 8 64wy bpp 8 or 16 The origin of the displayed coordinates has to be within the frame To be more specific the parameters are subject to the following constraints 0 DX w 64 8 bpp bpp 8 or 16 0 DY H DX DY and DA have to indicate t...

Page 381: ...ement of the palette is output to be displayed with 2 bits shifted toward the MSB side 18 6 3 2 Direct Color 16 bits pixel The level of each of RGB is expressed by 5 bits The basic precision of display output is 8 bits for each of RGB and the value of each color element is output to be displayed with 3 bits shifted toward the MSB side There are the ARGB and RGBA formats format 15 14 13 12 11 10 9 ...

Page 382: ...ch layer are shown below Layer Compatibility mode Extended mode L0 Direct color 16 24 Indirect color P0 Direct color 16 24 Indirect color P0 L1 Direct color 16 24 Indirect color P1 YCbCr Direct color 16 24 Indirect color P1 YCbCr L2 Direct color 16 24 Indirect color P1 Direct color 16 24 Indirect color P2 L3 Direct color 16 24 Indirect color P1 Direct color 16 24 Indirect color P3 L4 Direct color ...

Page 383: ... cursor 0 18 6 5 Display Scan Control 18 6 5 1 Applicable display The following table shows typical display resolutions and their synchronous signal frequencies The pixel clock frequency is determined by setting the division rate of the display reference clock The display reference clock is either the internal PLL e g 533 3 MHz at input frequency of 25 0 MHz or the clock supplied to the DCLKI inpu...

Page 384: ...s one screen When the DCM register synchronization mode is set to interlace 10 images in memory are output in raster order The same image data is output to odd fields and even fields Consequently the count of rasters on the screen is half of that of interlace video However unlike the non interlace mode there is a distinction between odd and even fields depending on the phase relationship between t...

Page 385: ...YCG1 b2 a23 L1YCB0 a32 a31 L1YCB1 b3 a33 Same conversion with previous products is applied by initial values of these registers after reset The register values just after reset is as follow a11 0x12b 299 256 a12 0x0 a13 0x198 408 256 a21 0x12b 299 256 a22 0x79c 100 256 a23 0x72f 209 256 a31 0x12b 299 256 a32 0x204 516 256 a33 0x0 b1 b2 b3 0x1f0 16 It is possible to control brightness contrast hue ...

Page 386: ...ameter 1 is standard 0 means mono chrome image c3 brightness parameter 0 is standard t hue rotation parameter 0 deg is standard Note new aij and bi should be clipped in valid range of value for corresponding registers 1 0 0 0 cos t sin t 0 sin t cos t A c1 A0 b bo c3 c3 c3 1 0 0 0 c2 0 0 0 c2 A0 c1 0 0 0 cos t c1c2 sin t c1c2 0 sin t c1c2 cos t c1c2 ...

Page 387: ...1C 14 PLL clocks 0x1E 15 PLL clocks 2 Inversion DCLKO inversion is also available with or without the delay functionality This function is effective without regard to the DCLK clock source The DCKinv bit of DCM3 enables this function 18 6 8 Synchronous register updates and display To update position related parameters without disturbing the display it is necessary to update in synch with the VSYNC...

Page 388: ...therefore different resolutions can be used by each controller and therefore each works asynchronously to the other VSYNC0 VSYNC1 interrupt interrupt The phase difference indicated above of each frame should be taken into consideration when drawing figures synchronously on two screens This assumes that the controllers have the same timing parameters and share the same clock source such as the inte...

Page 389: ...C register screen 1 screen 0 display device 0 display device 1 MB86R02 display controller 0 de mux Note Dual Display functionality is not possible with RSDS panels 18 6 10 2 Destination Control A layer or cursor can be included in both screens or one screen If a layer is NOT included in a screen this layer is treated as transparent If all the bits of a screen are set to 0 then the background color...

Page 390: ...uded 18 6 10 3 Output Signal Control Two screen data streams are output in multiplex mode as follows sc0 sc1 DRn DGn DBn DCLKOn HSYNCn even clocks DEn ref edge sc0 is first 18 6 10 4 Output Circuit Example A single CPLD can demultiplex the RGB 6bit component video data stream Xilinx device shown here DCKi VSi HSi Di 18 DCK0 VS0 HS0 D0 18 D0 17 0 Di 17 0 DRn 7 2 DGn 7 2 DBn 7 2 DCLKOn HSYNCn VSYNCn...

Page 391: ...HS0 VS0 DCK1 HS1 VS1 output 18 0 D0 D1 reg HS0 HS1 VS0 VS1 DCK0 DCK1 reg 18 0 D0 D1 always posedge DCKi begin HS0 HSi HS1 HS0 VS0 VSi VS1 VS0 DCK0 HS0 HSi 0 DCK0 sync to ref edge flip DCK1 DCK0 if DCK0 D0 Di if DCK1 D1 Di end endmodule Di DCLKi HSi even clocks ref edge sc0 sc1 sc0 sc1 sc1 sc0 sc0 sc1 sc1 DCK0 D0 18 0 DCK1 D1 18 0 read point read point ...

Page 392: ...able horizontal back porch 18 6 10 7 Dual display configuration example Single display In the case of a single display application set the DEN bit to 1 for the single display controller to be used Multiplex dual display mode has to be disabled The following example shows the settings for the use of display controller 0 only DCM1 DCM3 MDC DEN bit POM bit DCKed bit MDen bit SCnEN field DISP0 1 0 0 0...

Page 393: ...roller 1 in use in multiplex dual display mode DCM1 DCM3 MDC DEN bit POM bit DCKed bit MDen bit SCnEN field DISP0 1 0 0 0 Don t care DISP1 1 0 0 1 Valid Common VCCC dis2s 0 If two display controllers are used in multiplex dual display mode four display screens can be used 18 6 11 Video output limitation Due to the limited number of package pins the available video output is limitted as follows Dis...

Page 394: ... 8 SYNCERR1 of display 1 bit 9 REGUD1 of display 1 bit 10 Capture 0 bit 11 Capture 1 The host address offset of the IST register is 0x20 The offset address of the corresponding register for interrupt masking IMASK is 0x24 It has same bit allocation ...

Page 395: ...es BOB and WEAVE can be selected for non interlace transformation BOB Mode In odd fields the even field raster generated by average interpolation are added to produce one frame In even fields the odd field raster generated by average interpolation are added to produce one frame In order to choose BOB mode while enable vertical interpolation in VI bit of a VCM Video Capture Mode register the L1IM b...

Page 396: ...apture input port can be used for 656 format only whereby the other can select between RGB format and 656 format To use 656 input via the port which can handle both RGB and 656 check the pin multiplex tables in this Hardware Manual to obtain the details about external pin routing Use the VIS bit of the VCM register to select RGB or 656 input The input port is selected using the Csel0 1 bit of the ...

Page 397: ...ay controller 0 capture controller 0 capture controller 1 display controller 1 656 601 RGB 656 601 656 video RGB video display controller 0 capture controller 0 capture controller 1 display controller 1 656 RGB 656 601 601 is unavailable if RGB is used at another input 601 video 601 video display controller 0 capture controller 0 capture controller 1 display controller 1 656 601 RGB 656 601 ...

Page 398: ...ormat 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ARGB 16 bits pixel A R G B RGBA 16 bits pixel R G B A format 31 30 25 24 23 22 17 16 15 14 9 8 7 6 1 0 ARGB 24 bits pixel A ignored R G B RGBA 24 bits pixel R G B A The relationship between the capture data formats and the data format control bits in registers is shown below NRGB 1 CRGB 2 C24 2 RGBA Capture data format up scaling 0 0 0 0 YcbCr 16 bits pi...

Page 399: ...tem It displays one frame while the image data for another frame is being prepared in a memory If the frame rate of a video capture differs from that of a display then the continued ommission of the top of the display may occur 18 7 3 3 Area Allocation An application should allocate an area for about 2 2 frames as the video capture buffer This area size is about equivalent to the margin required f...

Page 400: ...8 7 3 5 Interlaced Display It is possible to display the picture saved in the video capture buffer in WEAVE mode i e interlaced When selected in register setup WEAVE mode uses an interlaced mechanism for video display and display scan However if the display scan is asynchronous motion scenes will produce a flickering effect In order to prevent this set the OO Odd Only bit of the CBM Capture Buffer...

Page 401: ...icient of 0x0968 in hexadecimal Reduction in horizontal direction 720 648 pixels 720 648 ratio of 1 111 1 111 2048 2275 filter coefficient of 0x08E3 in hexadecimal The result to be set in the CSC register is therefore 096808E3H The capture horizontal pixel CHP and capture vertical pixel CVP registers are used to limit the number of pixels output after scaling Note that they are not used to set sca...

Page 402: ...HP 0x00F0 240 decimal Note this value is derived by 480 2 2 pixel units Values for the CMDS Capture Magnify Display Size register CMDVL 0x01E0 480 decimal CMDHP 0x0140 320 decimal Note this value is derived by 640 2 2 pixel units Value for the L1WW L1 Layer Window Width register L1WW 0x0280 640 decimal Value for the L1WH L1 Layer Window Height register L1WH 0x01DF 479 decimal Note this value is de...

Page 403: ...h as Video processing for multimedia systems by Gerard de Haan I SBN 90 9014015 8 Eindhoven Sept 2000 The horizontal low pass filter consists of FIR filters finite impulse response filters with five taps Coefficients are specified in the CLPF Capture Low Pass Filter register CHLPF_Y Horizontal LPF Luminance element and RGB element coefficient code CHLPF_C Horizontal LPF chrominance element coeffic...

Page 404: ...chrominance Cb and Cr signal is done using bilinear interpolation BiLinear Interpolate method The interpolation filter processing of a Native RGB signal is done by cubic interpolation Cubic Interpolate method 4 Vertical low pass filter processing A preprocessing vertical low pass filter can be applied to an image before it is scaled down vertically The vertical LPF can be activated regardless of w...

Page 405: ...ster CSC are used for both vertical downscale and upscale processing The vertical downscaling of an incoming data stream is done before writing to VRAM Upscaling in the vertical direction is done after reading from VRAM The interpolation filter processing of the luminance Y signal is done using cubic interpolation Cubic Interpolate method The interpolation filter processing of chrominance Cb and C...

Page 406: ...t error codes use the VS Video Select bit of the VCM register to specify whether the input is an NTSC or PAL signal If NTSC is set specify the data count in the capture data count register CDCN If PAL is set specify the data count in the capture data counter register CDCP If the data count does not match the data stream then bits 4 to bit 0 of the video capture status register VCS will contain val...

Page 407: ...0 80 1 0 0 0 0 0 0 0 9D 1 0 0 1 1 1 0 1 AB 1 0 1 0 1 0 1 1 B6 1 0 1 1 0 1 1 0 C7 1 1 0 0 0 1 1 1 DA 1 1 0 1 1 0 1 0 EC 1 1 1 0 1 1 0 0 F1 1 1 1 1 0 0 0 1 80 SAV code of first field valid pixel period active video 9D EAV code of first field valid pixel period active video AB SAV code of first field vertical retrace line period B6 EAV code of first field vertical retrace line period C7 SAV code of s...

Page 408: ...I1_2 Input Green component value BI1_7 BI1_2 Input Blue component value VINVSYNC1 Input Vertical sync for RGB capture HINVSYNC1 Input Horizontal sync for RGB capture Note 1 Input pins are shared with the ITU656 input and memory data bus Note 2 The VIS bit of the VCM video capture mode register selects which mode RBT ITU656 601 or RGB is used 2 Captured Range In comparison to the embedded sync code...

Page 409: ...t Matrix Coefficient In order to change the color conversion matrix configure RGBCMY RGBCb RGBCr and RGBCMb Note The maximum horizontal enable area size RGBHEN which can be captured is 840 pixels This restriction is due to the line buffer size in each video capture module 18 7 5 3 Input Operation When handling RGB input the synchronization of data is realized using the VSYNC and SYNCI signals whic...

Page 410: ...sing HSYNC and a clock could have line jitter CCLK1 HSYNCI RI5 0 GI5 0 BI5 0 RGBHST captured 3 VINVSYNC Polarity and Rules A VSYNCI signal is in sync with HSYNCI VSYNCI is sampled by HSYNCI and is used as a VSYNC signal Its width is at least one line or more although a VSYNCI signal does not need to synchronize with HSYNC at this time Both the positive and negative edges of VSYNCn can be used as a...

Page 411: ...onverted to YCbCr using the following matrix operation Y a11 R a12 G a13 B b1 Cb a21 R a22 G a23 B b2 aij 10bit signed real the lower 8 bits are the fraction Cr a31 R a32 G a33 B b3 bi 8bit unsigned integer Note 1 Registers can define each coefficient Note 2 Cb and Cr components are halved after this operation for the 4 2 2 format ...

Page 412: ...e video format which is input Registers that must be configured are shown in the following figure VIS RGBHC RGBHST RGBHEN RGBVST RGBVEN RM VP HP RGBCMY RGBCMCb RGBCMCr RGBCMb RGBHC RGBHST RGBHEN RGBVST RGBVEN RM VP HP RGBCMY VS ITU R BT656 NRGB Native RGB 0 1 0 1 RGB 656 Figure 8 2 Registers to be configured according to the input format ...

Page 413: ...eAddress DisplayBase0 0xF1FD_0000 or DisplayBase1 0xF1FD_2000 Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 000 DCM0 Display Control Mode 0 DEN L45E L23E L1E L0E CKS LCS SC EEQ EDE EOF EOD SF ESY SYNC 100 DCM1 Display Control Mode 1 DEN L5E L4E L3E L2E L1E L0E CKS LCS SC EEQ EDE EOF EOD SF ESY SYNC 104 DCM2 Display Control Mode 2 RUM1 RUF RUM0 108 DCM...

Page 414: ...e L1C L1YC L1CS L1IM L1S L1 Stride 034 L1OA0 L1 Origin Address 0 CBDA0 Capure Buffer Display Address 0 038 CBDA1 Capture Buffer Display Address 1 120 L1EM L1 Extend Mode L1EC L1CP VMAG L1PB 124 L1WY L1 Window Y L1WX L1 Window X 128 L1WH L1 Window Height L1WW L1 Window Width 040 L2M L2 Mode L2C L2FLP L2S L2 Stride L0H L0 Height 044 L2OA0 L2 Origin Address 0 048 L2DA0 L2 Display Address 0 04C L2OA1 ...

Page 415: ...070 L4M L4 Mode L4C L4FLP L4S L4 Stride L4H L4 Height 074 L4OA0 L4 Origin Address 0 078 L4DA0 L4 Display Address 0 07C L4OA1 L4 Origin Address 1 080 L4DA1 L4 Display Address 1 084 L4DY L4 Display Y L4DX L4 Display X 150 L4EMv0 L4 Extend Mode L4EC L4OM L4WP 154 L4WY L4 Window Y L4WX L4 Window X 158 L4WH L4 Window Height L4WW L4 Window Width 088 L5M L5 Mode L5C L5FLP L5S L5 Stride L5H L5 Height 08C ...

Page 416: ...ress 0B0 CUY1 Cursor1 Position Y CUX1 Cursor1 Position X 170 MDC Multi Display Control MDEN SC1EN SC0EN 180 DLS Display Layer Select DLS5 DLS4 DLS3 DLS2 DLS1 DLS0 184 DBGC Display Back Ground Color 0B4 L0BLD L0 Blend L0BE L0BS L0BI L0BP L0ID res res L0BR 188 L1BLD L1 Blend L1BE L1BS L1BI L1BP L1ID res res L1BR 18C L2BLD L2 Blend L2BE L2BS L2BI L2BP L2ID res res L2BR 190 L3BLD L3 Blend L3BE L3BS L3...

Page 417: ...ol L1EZT L1ETC L1 Extend Transparent Color 1A8 L2TEC L2 Transparent Extend Control L2EZT L2ETC L2 Extend Transparent Color 1AC L3TEC L3 Transparent Extend Control L0EZT L3ETC L3 Extend Transparent Color 1B0 L4ETC L4 Extend Transparent Control L4EZT L4ETC L4 Extend Transparent Color 1B4 L5ETC L5 Extend Transparent Control L5EZT L5ETC L5 Extend Transparent Color 1E0 L1YCR0 L1 YC to Red Coefficient 0...

Page 418: ... 6 5 4 3 2 1 0 400 L0PAL0 A R G B 404 L0PAL1 7FC L0PAL255 800 L1PAL0 A R G B 804 L1PAL1 BFC L1PAL255 1000 L2PAL0 A R G B 1004 L2PAL1 13FC L2PAL255 1400 L3PAL0 A R G B 1404 L3PAL1 17FC L3PAL255 1C00 VPWMM Video PWM Mde EN INV VSYR HSYR ENDR HSYB 1C04 VPWME Video PWM End VPWMS Video PWM Start 1C08 HOLD VPWMC Video PWM Count ...

Page 419: ...ture Buffer Mode OOM SBUF CRGB CBW stride C24 CBST 014 CBOA Capture Buffer Origin Address 018 CBLA Capture Buffer Limit Address 01C CIVSTR CIHSTR 020 CIVEND CIHEND 028 CHP Capture Horizontal Pixel CHP 02C CVP Capture Vertical Pixel CVPP CVPN 048 CMSS Capture Magnify Source Size CMSHP CMSVL 040 CLPF Capture Low Pass Filter CVLPF CHLPF 04C CMDS Capture Magnify Display Size CMDHP CMDVL 080 RGBHC RGB ...

Page 420: ... RGBCMY RGB Color convert Matrix Y coefficient a11 a12 a13 0C4 RGBCMCb RGB Color convert Matrix Cb coefficient a21 a22 a23 0C8 RGBCMCr RGB Color convert Matrix Cr coefficient a31 a32 a33 0CC RGBCMb RGB Color convert Matrix b coefficient b1 b2 b3 4000 CDCN Capture Data Count for NTSC BDCN VDCN 4004 CDCP Capture Data Count for PAL BDCP VDCP ...

Page 421: ...read write of each field Each symbol shown in this section denotes the following R0 0 always read at read Write access is Don t care W0 Only 0 can be written R Read enabled W Write enabled RX Read enabled read values undefined RW Read and write enabled RW0 Read and write 0 enabled 5 Initial value Indicates initial value of immediately before the reset of each bit field X means no deterministic val...

Page 422: ...to perform software reset for display controller 1 Reset action is triggered by write of VCSR register It is only specifying that this bit is written 0 Performs no software reset 1 Performs software reset Bit 2 C0sr Capture0 software reset Specifies whether or not to perform software reset for capture controller 0 Reset action is triggered by write of VCSR register It is only specifying that this ...

Page 423: ... Apix capture 1 select Selects Apix input for capture controller 1 0 RGB 656 shared port 1 Apix ch 1 Bit 17 hmon host monitor This specifies a debug function that displays data access of host CPU on screen Upper hexadecimal value means address and lower one means data 0 disable 1 enable Bit 20 dis2s display two select Specifies use of internal demultiplexer for multiplex dual display mode 0 Two vi...

Page 424: ...RW RW RW RW RW RW RW RW RW RW R0 RW RW RW Initial value 0 0 X 0 0 0 0 0 0 0 0 11101 0 0 0 0 0 0 00 This register controls the display count mode It is not initialized by a software reset This register is mapped to two addresses but it is one substance The differences between the two registers are the format of the frequency division rate setting SC and layer enable The two formats exist to maintai...

Page 425: ...is set to the SC field with Offset 0 2n 1 is reflected with Offset 100h Also when PLL is selected as the reference clock frequency division rates 1 1 to 1 5 are non functional even when set other frequency division rates are assigned Bit 14 LCS Lower Frequency Clock Select Predivide the clock signal for the dot clock 0 The clock source for the scaler is the internal PLL clock 1 The clock source fo...

Page 426: ...ous display of the L4 and L5 layers These layers correspond to the B layer for previous products 0 Does not display L4 and L5 layer 1 Displays L4 and L5 layer L3E L3 layer Enable DCM1 Enables L3 layer display 0 Does not display L3 layer 1 Displays L3 layer Bit 20 L4E L4 layer Enable Enables L4 layer display 0 Does not display L4 layer 1 Displays L4 layer Bit 21 L5E L5 layer Enable Enables L5 layer...

Page 427: ...g with vertical synchronization is selected 0 The register update is done in internal control circuit real time The display is disturbed if an update occurs in the display period 1 The value of the register propagates through the internal control circuit in sync with vertical synchronization This syncing is controlled using the RUF flag Bit1 RUF Register Update Flag The value is scheduled to be up...

Page 428: ...output signal is inverted Bit9 DCKed Display clock edge 2 This defines which edge mode is used 0 single edge mode in which positive edge is used for digital RGB output 1 bi edge mode in which positive edge and negative edge are used for digital RGB output to identify two data streams Bit10 POM Parallel output Mode This defines a way to output two data streams for two display 0 multiplex output mod...

Page 429: ...on is intended for debugging purposes 0 no reverse 1 reverse bit order of RGB output Bit22 CSY0 CSYNC output zero If CSYNC output is connected to external DAC input for sync on green this bit can be used as sync on green disable 0 CSYNC singal is valid 1 CSYNC signal is fixed to zero therefore sync on green is disabled Refer to the specification of the connected DAC Bit24 VPWMs Video sync PWM sele...

Page 430: ... X This register controls the display period of the left part of the window in unit of pixel clocks Setting value 1 is the pixel count for the display period of the left part of the window When the window is not divided into right and left before display set the same value as HDP HSP Horizontal Synchronize pulse Position Register address DisplayBaseAddress 0x0C Bit number 15 14 13 12 11 10 9 8 7 6...

Page 431: ...lay Setting value 1 5 is the total raster count for 1 field 2 setting value 3 is the total raster count for 1 frame see Section 8 3 2 VSP Vertical Synchronize pulse Position Register address DisplayBaseAddress 0x14 Bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved VSP R W R0 RW Initial value 0 X This register controls the pulse position of vertical synchronization signal in ...

Page 432: ...direct color 8 bits pixel mode ARGB 1 Direct color 16 bits pixel mode ARGB L0EM L0 layer Extended Mode Register address DisplayBaseAddress 0x110 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 4 3 2 1 0 Bit field name L0EC Reserved L0PB Reserved L0WP R W RW R0 RW R0 RW Initial value 0 0 0 Bit 0 L0 WP L0 layer Window Position enable Selects the display position of L0 la...

Page 433: ... register sets the display origin address of the L0 layer For the direct color mode 16 bits pixel the lower 1 bit is 0 and this address is treated as being aligned in 2 bytes L0DX L0 layer Display position X Register address DisplayBaseAddress 0x2C Bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L0DX R W R0 RW Initial value 0 X This register sets the display starting posit...

Page 434: ...ial value 0 X This register sets the Y coordinates of the display position of the L0 layer window L0WW L0 layer Window Width Register address DisplayBaseAddress 0x118 Bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L0WW R W R0 RW Initial value 0 X This register controls the horizontal direction display size width of the L0 layer window Do not specify 0 L0WH L0 layer Window...

Page 435: ... capture mode when L1CS in capture mode 0 Normal mode 1 For non interlace display displays captured video graphics in WEAVE mode For interlace and video display buffers are managed in frame units pair of odd field and even field Bit 29 L1CS L1 layer Capture Synchronize Sets whether the layer is used as normal display layer or as video capture 0 Normal mode 1 Capture mode Bit 30 L1YC L1 layer YC mo...

Page 436: ...ress DisplayBaseAddress 0x34 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L1DA R W R0 RW Initial value 0 X This register sets the display origin address of the L1 layer For the direct color mode 16 bits pixel the lower 1 bit is 0 and this register is treated as being aligned in 2 bytes Wraparound processing is not performe...

Page 437: ...splayBaseAddress 0x128 DisplayBaseAddress 0x1C Bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L1WW R W R0 RW Initial value 0 X This register controls the horizontal direction display size width of the L1 layer window Do not specify 0 L1WH L1 layer Window Height Register address DisplayBaseAddress 0x12A DisplayBaseAddress 0x1E Bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1...

Page 438: ...e height of the logic frame of the L2 layer in pixel units Setting value 1 is the height Bit 23 to 16 L2W L2 layer memory Width Sets the memory width stride of the logic frame of the L2 layer in 64 byte units Bit 30 and 29 L2FLP L2 layer Flip mode Sets flipping mode for L2 layer 00 Displays frame 0 01 Displays frame 1 10 Switches frame 0 and 1 alternately for display 11 Reserved Bit 31 L2C L2 laye...

Page 439: ...nable Selects the display position of L2 layer 0 Compatibility mode display ML layer supported 1 Window display Bit 1 L2OM L2 layer Overlay Mode Selects the overlay mode for L2 layer 0 Compatibility mode 1 Extended mode Bit 23 to 20 L2PB L2 layer Palette Base Shows the value added to the index when subtracting palette of L2 layer 16 times of setting value is added Bit 31 and 30 L2EC L2 layer Exten...

Page 440: ...ister address DisplayBaseAddress 0x4C Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name L2OA1 R W RW RW0 Initial value X This register sets the origin address of the logic frame of the L2 layer in frame 1 Since lower 4 bits are fixed to 0 this address is 16 byte aligned L2DA1 L2 layer Display Address 1 Register address DisplayBaseAddres...

Page 441: ... Window position Y Register address DisplayBaseAddress 0x136 Bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L2WY R W R0 RW Initial value 0 Don t care This register sets the Y coordinates of the display position of the L2 layer window L2WW L2 layer Window Width Register address DisplayBaseAddress 0x138 Bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserve...

Page 442: ...e height of the logic frame of the L3 layer in pixel units Setting value 1 is the height Bit 23 to 16 L3W L3 layer memory Width Sets the memory width stride of the logic frame of the L3 layer in 64 byte units Bit 30 and 29 L3FLP L3 layer Flip mode Sets flipping mode for L3 layer 00 Displays frame 0 01 Displays frame 1 10 Switches frame 0 and 1 alternately for display 11 Reserved Bit 31 L3C L3 laye...

Page 443: ...able Selects the display position of L3 layer 0 Compatibility mode display MR layer supported 1 Window display Bit 1 L3OM L3 layer Overlay Mode Selects the overlay mode for L3 layer 0 Compatibility mode 1 Extended mode Bit 23 to 20 L3PB L3 layer Palette Base Shows the value added to the index when subtracting palette of L3 layer 16 times of setting value is added Bit 31 and 30 L3EC L3 layer Extend...

Page 444: ...ister address DisplayBaseAddress 0x64 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name L3OA1 R W RW RW0 Initial value X This register sets the origin address of the logic frame of the L3 layer in frame 1 Since lower 4 bits are fixed to 0 this address is 16 byte aligned L3OA1 L3 layer Display Address 1 Register address DisplayBaseAddres...

Page 445: ...layer Window position Y Register address DisplayBaseAddress 0x146 Bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L3WY R W R0 RW Initial value 0 X This register sets the Y coordinates of the display position of the L3 layer window L3WW L3 layer Window Width Register address DisplayBaseAddress 0x148 Bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L3...

Page 446: ...s the height of the logic frame of the L4 layer in pixel units Setting value 1 is the height Bit 23 to 16 L4W L4 layer memory Width Sets the memory width stride logic frame of the L4 layer in 64 byte units Bit 30 and 29 L4FLP L4 layer Flip mode Sets flipping mode for L4 layer 00 Displays frame 0 01 Displays frame 1 10 Switches frame 0 and 1 alternately for display 11 Reserved Bit 31 L4C L4 layer C...

Page 447: ...nable Selects the display position of L4 layer 0 Compatibility mode display BL layer supported 1 Window display Bit 1 L4OM L4 layer Overlay Mode Selects the overlay mode for L4 layer 0 Compatibility mode 1 Extended mode Bit 23 to 20 L4PB L4 layer Palette Base Shows the value added to the index when subtracting palette of L4 layer 16 times of setting value is added Bit 31 and 30 L4EC L4 layer Exten...

Page 448: ...1 Register address DisplayBaseAddress 0x7C Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name L4OA1 R W RW RW0 Initial value X This register sets the origin address of the logic frame of the L4 layer in frame 1 Since lower 4 bits are fixed to 0 this address is 16 byte aligned L4OA1 L4 layer Display Address 1 Register address DisplayBaseA...

Page 449: ...layer Window position Y Register address DisplayBaseAddress 0x156 Bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L4WY R W R0 RW Initial value 0 X This register sets the Y coordinates of the display position of the L4 layer window L4WW L4 layer Window Width Register address DisplayBaseAddress 0x158 Bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L4...

Page 450: ...s the height of the logic frame of the L5 layer in pixel units Setting value 1 is the height Bit 23 to 16 L5W L5 layer memory Width Sets the memory width stride logic frame of the L5 layer in 64 byte units Bit 30 and 29 L5FLP L5 layer Flip mode Sets flipping mode for L5 layer 00 Displays frame 0 01 Displays frame 1 10 Switches frame 0 and 1 alternately for display 11 Reserved Bit 31 L5C L5 layer C...

Page 451: ...able Selects the display position of L5 layer 0 Compatibility mode display BR layer supported 1 Window display Bit 1 L5OM L5 layer Overlay Mode Selects the overlay mode for L5 layer 0 Compatibility mode 1 Extended mode Bit 23 to 20 L5PB L5 layer Palette Base Shows the value added to the index when subtracting palette of L5 layer 16 times of setting value is added Bit 31 to 30 L5EC L5 layer Extende...

Page 452: ...ister address DisplayBaseAddress 0x94 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name L5OA1 R W RW RW0 Initial value X This register sets the origin address of the logic frame of the L5 layer in frame 1 Since lower 4 bits are fixed to 0 this address is 16 byte aligned L5OA1 L5 layer Display Address 1 Register address DisplayBaseAddres...

Page 453: ...layer Window position Y Register address DisplayBaseAddress 0x166 Bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L5WY R W R0 RW Initial value 0 X This register sets the Y coordinates of the display position of the L5 layer window L5WW L5 layer Window Width Register address DisplayBaseAddress 0x168 Bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L5...

Page 454: ...Bit number 7 6 5 4 3 2 1 0 Bit field name Reserved CEN1 CEN0 Reserved CUO1 CUO0 R W R0 RW RW R0 RW RW Initial value 0 0 0 0 0 0 This register controls the display priority of cursors Cursor 0 is always preferred to cursor 1 Bit 0 CUO0 Cursor Overlap 0 Sets display priority between cursor 0 and pixels of Console layer 0 Puts cursor 0 at lower than L0 layer 1 Puts cursor 0 at higher than L0 layer Bi...

Page 455: ...ess DisplayBaseAddress 0xA8 Bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved CUX0 R W R0 RW Initial value 0 X This register sets the display position X coordinates of the cursor 0 in pixels The reference position of the coordinates is the top left of the cursor pattern CUY0 Cursor 0 Y position Register address DisplayBaseAddress 0xAA Bit number 15 14 13 12 11 10 9 8 7 6 5 4...

Page 456: ...ess DisplayBaseAddress 0xB0 Bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved CUX1 R W R0 RW Initial value 0 X This register sets the display position X coordinates of the cursor 1 in pixels The reference position of the coordinates is the top left of the cursor pattern CUY1 Cursor 1 Y position Register address DisplayBaseAddress 0xB2 Bit number 15 14 13 12 11 10 9 8 7 6 5 4...

Page 457: ... included into screen 0 1 L1 is included into screen 0 Bit 5 SC0en5 screen 0 enable 5 0 L5 is not included into screen 0 1 L5 is included into screen 0 Bit 6 SC0en6 screen 0 enable 6 0 Cursor0 is not included into screen 0 1 Cursor0 is included into screen 0 Bit 7 SC0en7 screen 0 enable 7 0 Cursor1 is not included into screen 0 1 Cursor1 is included into screen 0 Bit 8 SC1en0 screen 1 enable 0 0 L...

Page 458: ...s not included into screen 1 1 Cursor 0 is included into screen 1 Bit 15 SC1en7 screen 1 enable 7 0 Cursor 1 is not included into screen 1 1 Cursor 1 is included into screen 1 Bit 31 MDen multi display enable This enables multi or dual display mode 0 Single display mode 1 Dual display mode ...

Page 459: ...r 0001 L1 layer 0101 L5 layer 0110 Reserved 0110 Reserved 0111 Not selected Bit 7 to 4 DSL1 Display Layer Select 1 Selects the second layer subjected to blending The bit values are the same as DSL0 Bit 11 to 8 DSL2 Display Layer Select 2 Selects the third layer subjected to blending The bit values are the same as DSL0 Bit 15 to 12 DSL3 Display Layer Select 3 Selects the fourth layer subjected to b...

Page 460: ...erved DBGR DBGG DBGB R W R0 Initial value This register specifies the color to be displayed in areas outside the display area of each layer on the window Bit 7 to 0 DBGB Display Background Blue Specifies the blue level of the background color Bit 15 to 8 DBGG Display Background Green Specifies the green level of the background color Bit 23 to 16 DBGR Display Background Red Specifies the red level ...

Page 461: ...lend plane 0 Value of L0BR used as blend ratio 1 Pixel of L5 layer used as blend ratio Bit 14 L0BI L0 layer Blend Increment Selects whether or not 1 256 is added when the blend ratio is not 0 0 Blend ratio calculated as is 1 1 256 added when blend ratio 0 Bit 15 L0BS L0 layer Blend Select Selects the blend calculation expression 0 Upper image Blend ratio Lower image 1 Blend ratio 1 Upper image 1 B...

Page 462: ...s blend ratio 1 Pixel of L5 layer used as blend ratio Bit 14 L1BI L1 layer Blend Increment Selects whether or not 1 256 is added when the blend ratio is not 0 0 Blend ratio calculated as is 1 1 256 added when blend ratio 0 Bit 15 L1BS L1 layer Blend Select Selects the blend calculation expression 0 Upper image Blend ratio Lower image 1 Blend ratio 1 Upper image 1 Blend ratio Lower image Blend rati...

Page 463: ...s blend ratio 1 Pixel of L5 layer used as blend ratio Bit 14 L2BI L2 layer Blend Increment Selects whether or not 1 256 is added when the blend ratio is not 0 0 Blend ratio calculated as is 1 1 256 added when blend ratio 0 Bit 15 L2BS L2 layer Blend Select Selects the blend calculation expression 0 Upper image Blend ratio Lower image 1 Blend ratio 1 Upper image 1 Blend ratio Lower image Blend rati...

Page 464: ...s blend ratio 1 Pixel of L5 layer used as blend ratio Bit 14 L3BI L3 layer Blend Increment Selects whether or not 1 256 is added when the blend ratio is not 0 0 Blend ratio calculated as is 1 1 256 added when blend ratio 0 Bit 15 L3BS L3 layer Blend Select Selects the blend calculation expression 0 Upper image Blend ratio Lower image 1 Blend ratio 1 Upper image 1 Blend ratio Lower image Blend rati...

Page 465: ...s blend ratio 1 Pixel of L5 layer used as blend ratio Bit 14 L4BI L4 layer Blend Increment Selects whether or not 1 256 is added when the blend ratio is not 0 0 Blend ratio calculated as is 1 1 256 added when blend ratio 0 Bit 15 L4BS L4 layer Blend Select Selects the blend calculation expression 0 Upper image Blend ratio Lower image 1 Blend ratio 1 Upper image 1 Blend ratio Lower image Blend rati...

Page 466: ...Increment Selects whether or not 1 256 is added when the blend ratio is not 0 0 Blend ratio calculated as is 1 1 256 added when blend ratio 0 Bit 15 L5BS L5 layer Blend Select Selects the blend calculation expression 0 Upper image Blend ratio Lower image 1 Blend ratio 1 Upper image 1 Blend ratio Lower image Blend ratio Bit 16 L5BE L5 layer Blend Enable This bit enables blending 0 Overlay via trans...

Page 467: ...sed Bit 15 L0ZT L0 layer Zero Transparency Sets handling of color code 0 in L0 layer 0 Code 0 as transparency color 1 Code 0 as non transparency color L2TC L2 layer Transparency Control Register address DisplayBaseAddress 0xC2 Bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name L2ZT L2TC R W RW RW Initial value 0 Don t care This register sets the transparent color for the L2 layer When...

Page 468: ... 1 Code 0 as non transparency color L0ETC L0 layer Extend Transparency Control Register address DisplayBaseAddress 0x1A0 Bit number 31 30 29 28 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name L0ETZ Reserved L0TEC R W RW R0 RW Initial value 0 0 This register sets the transparent color for the L0 layer The 24 bits pixel transparent color is set using this register The...

Page 469: ...ts handling of color code 0 in L1 layer 0 Code 0 as transparency color 1 Code 0 as non transparency color L2ETC L2 layer Extend Transparency Control Register address DisplayBaseAddress 0x1A8 Bit number 31 30 29 28 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name L2ETZ Reserved L2TEC R W RW R0 RW Initial value This register sets the transparent color for the L2 layer ...

Page 470: ...xel bits 7 to 0 are used Bit 31 L3EZT L3 layer Extend Zero Transparency Sets handling of color code 0 in L3 layer 0 Code 0 as transparency color 1 Code 0 as non transparency color L4ETC L4 layer Extend Transparency Control Register address DisplayBaseAddress 0x1B0 Bit number 31 30 29 28 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name L4ETZ Reserved L4TEC R W RW R0 R...

Page 471: ...s register sets the transparent color for the L5 layer This register sets the transparent color for the L5 layer When L5ETC 0 and L5EZT 0 color 0 is displayed in black transparent Bit 23 to 0 L5ETC L5 layer Extend Transparent Color Sets transparent color code for the L5 layer In indirect color mode 8 bits pixel bits 7 to 0 are used Bit 31 L5EZT L5 layer Extend Zero Transparency Sets handling of co...

Page 472: ...lower 8bit is fraction two s complement Bit 26 to 16 a12 11bit signed real lower 8bit is fraction two s complement Refer 7 7 for detail L1YCR1 L1 layer YC to Red coefficient 1 Register address DisplayBaseAddress 0x1E4 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved b1 Reserved a13 R W R0 RW R0 RW Initial value 0 1 1111 0000 0...

Page 473: ...lower8bit is fraction two s complement Bit 26 to 16 a22 11bit signed real lower 8bit is fraction two s complement Refer 7 7 for detail L1YCG1 L1 layer YC to Green coefficient 1 Register address DisplayBaseAddress 0x1EC Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved b2 Reserved a23 R W R0 RW R0 RW Initial value 0 1 1111 0000 ...

Page 474: ...lower 8bit is fraction two s complement Bit 26 to 16 a32 11bit signed real lower 8bit is fraction two s complement Refer 7 7 for detail L1YCB1 L1 layer YC to Blue coefficient 1 Register address DisplayBaseAddress 0x1F4 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved b3 Reserved a33 R W R0 RW R0 RW Initial value 0 1 1111 0000 ...

Page 475: ...or mode a color code in the display frame indicates the palette register number and the color information set in that register is applied as the display color of that pixel This register corresponds to the CPALn register for previous products Bit 7 to 2 B Blue Sets blue color component Bit 15 to 10 G Green Sets green color component Bit 23 to 18 R Red Sets red color component Bit 31 A Alpha Specif...

Page 476: ...or mode a color code in the display frame indicates the palette register number and the color information set in that register is applied as the display color of that pixel This register corresponds to the MBPALn register for previous products Bit 7 to 2 B Blue Sets blue color component Bit 15 to 10 G Green Sets green color component Bit 23 to 18 R Red Sets red color component Bit 31 A Alpha Speci...

Page 477: ...ayer and cursors In the indirect color mode a color code in the display frame indicates the palette register number and the color information set in that register is applied as the display color of that pixel Bit 7 to 2 B Blue Sets blue color component Bit 15 to 10 G Green Sets green color component Bit 23 to 18 R Red Sets red color component Bit 31 A Alpha Specifies whether or not to perform blen...

Page 478: ...ayer and cursors In the indirect color mode a color code in the display frame indicates the palette register number and the color information set in that register is applied as the display color of that pixel Bit 7 to 2 B Blue Sets blue color component Bit 15 to 10 G Green Sets green color component Bit 23 to 18 R Red Sets red color component Bit 31 A Alpha Specifies whether or not to perform blen...

Page 479: ... Native RGB Bit20 VI Vertical Interpolation Sets whether to perform vertical interpolation 0 Performs vertical interpolation The graphics are enlarged vertically by two times 1 Does not perform vertical interpolation Bit25 24 CM Capture Mode Sets video capture mode To capture vides set these bits to 11 00 Initial value 01 Reserved 10 Reserved 11 Capture Bit28 VICE Video Input Clock Enable Capture ...

Page 480: ...18 122 MB86R02 Jade D Hardware Manual V1 64 2 1 is written in bit31 VIE of the VCM register and the video capture function is made effective ...

Page 481: ... of a horizontal upscaling downscaling ratio is set Bit15 11 HSCI Horizontal Scale Integer The integer part of a horizontal upscaling downscaling ratio is set Bit26 16 VSCF Vertical SCale Fraction The decimal part of a vertical upscaling downscaling ratio is set Bit31 27 VSCI Vertical SCale Integer The integer part of a vertical upscaling downscaling ratio is set Note Smooth continuation operation...

Page 482: ...le endian enable display 1 Big endian disable display Bit14 C24 Color 24bit pixel It specifies wherther 24bit pixel or 16bit pixel is used in RGB capture It is effective in native RGB capture NRGB 1 or converted RGB capture CRGB 1 0 16bit pixel 1 24bit pixel Bit23 16 CBW Capture Buffer memory Width Sets memory width stride of capture buffer in 64 bytes Bit28 PAU PAUse It is shown that capture oper...

Page 483: ...W R0 Initial value Don t care 0 This register specifies the starting origin address of the video capture buffer CBLA video Capture Buffer Limit Address Register address CaptureBaseAddress 18h Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name CBLA R W R W R0 Initial value Don t care 0 This register specifies the end limit address of the ...

Page 484: ... the top left of the image For downscaling apply this setting to the post reduction image coordinates Note The even number is set at the YUV mode CIVSTR Capture Image Vertical STaRt Register address CaptureBaseAddress 1Eh Bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved CIVSTR R W RX R W Initial value Don t care Don t care This register sets the range of the images to be wr...

Page 485: ... the YUV mode horizontal pixel size CIHEND CIHSTR sets the even number CIVEND Capture Image Vertical END Register address CaptureBaseAddress 22h Bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved CIVEND R W RX R W Initial value X X This register sets the range of the images to be written captured to the video capture buffer Specify the Y coordinates located in the bottom righ...

Page 486: ...alue is 0x1A4 CVP Capture Vertical Pixel Register address CaptureBaseAddress 2cH Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved CVPP Reserved CVPN R W RX RW RX RW Initial value X 271H 625D X 20DH 525D This register sets the count of vertical pixels of the image output after scaling The fields to be used depend on the video f...

Page 487: ...7 to 16 CHLPF_C Capture Horizontal LPF coefficient C CHLPF_C K0 K1 K2 K3 K4 00 0 0 1 0 0 01 0 1 4 2 4 1 4 0 10 0 3 16 10 16 3 16 0 11 3 32 8 32 10 32 10 32 3 32 Bit 19 to 18 CHLPF_Y Capture Horizontal LPF coefficient Y CHLPF_Y K0 K1 K2 K3 K4 00 0 0 1 0 0 01 0 1 4 2 4 1 4 0 10 0 3 16 10 16 3 16 0 11 3 32 8 32 10 32 10 32 3 32 Bit 25 to 24 CVLPF_C Capture Vertical LPF coefficient C CVLPF_C K0 K1 K2 ...

Page 488: ...7 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved CMDHP Reserved CMDVL R W RX R W RX R W Initial value X X X X Bit11 0 CMDVL Capture Magnify Display Vertical Line This register sets the number of vertical lines of the image output after Magnify scaling Bit27 16 CMDHP Capture Magnify Display Horizontal Pixel This register sets the number of horizontal pixels of the image output aft...

Page 489: ...nable area Size Effective pixel data size is set up per pixel Specify the number of horizontal pixels in 2 pixel units Bit27 16 RGBHST RGB input Horizontal Enable area Start position The start position of effective pixel data is set up The setting value 4 is a start position Note The maximum horizontal enable area size RGBHEN which can be captured is 840 pixels This is the restriction by line buff...

Page 490: ...R W RX R W R W Initial value X 1 X 0 0 Edge detection of a synchronized signal is set up It is used at the time of RGB input format Bit0 VP VSYNCI Polarity 0 Negative edge of VINVSYNC is set to VSYNC 1 Positive edge of VINVSYNC is set to VSYNC Bit1 HP HSYNCI Polarity 0 Negative edge of VINHSYNC is set to HSYNC 1 Positive edge of VINHSYNC is set to HSYNC Bit16 RM RGB Input Mode select Sets Direct R...

Page 491: ...ame a11 Re a12 Re a13 R W RW R RW R RW Initial value 0001000010 b 0 0010000000 b 0 0000011001 b This register sets the RGB color convert matrix coefficient Bit 31 to 22 a11 10bit signed real lower8bit is fraction Bit 20 to 11 a12 10bit signed real lower8bit is fraction Bit 9 to 0 a13 10bit signed real lower8bit is fraction RGBCMCb RGB Color convert Matrix Cb coefficient Register address CaptureBas...

Page 492: ...nt Bit 31 to 22 A31 10bit signed real lower8bit is fraction Bit 20 to 11 A32 10bit signed real lower8bit is fraction Bit 9 to 0 A33 10bit signed real lower8bit is fraction RGBCMb RGB Color convert Matrix b coefficient Register address CaptureBaseAddress CCH Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name R B1 Res b2 Res b3 R W R RW R ...

Page 493: ...Count for NTSC Sets count of data processed during valid period in NTSC format The setting value 1 is a data number Bit28 16 BDCN Blanking Data Count for NTSC Sets count of data processed during blanking period in NTSC format The setting value 1 is a data number The range of VDCN and BDCN is shown in the following figure SAV start of active video timing reference code EAV end of active video timin...

Page 494: ...ved BDCP Reserved VDCP R W RX RW RX RW Initial value X 0x11B 283 X 0x5A3 1443 This register sets the count of data of the input video stream in PAL format Bit12 0 VDCP Valid Data Count for PAL Sets count of data processed during valid period in PAL format The setting value 1 is a data number Bit28 16 BDCP Blanking Data Count for PAL Sets count of data processed during blanking period in PAL format...

Page 495: ...the number of data in the capture data count register CDCN If PAL is set reference the number of data in the capture data counter register CDCP If the reference data does not match the stream data or undefined Fourth word of SAV EAV codes are detected bits 4 to 0 of the video capture status register VCS will be values as follows Bits 6 0 CE0 Capture Error 0 Bit0 1 RBT 656 undefined error Code Bit7...

Page 496: ...DISPE Ri Gi Bi DISPE DCLKO 0 1 2 n 1 n 2 n HDP 1 Ri Gi Bi Non interlace Timing In the above diagram VTR HDP etc are the setting values of their associated registers The VSYNC frame interrupt is asserted when display of the last raster ends When updating display parameters synchronize with the frame interrupt so no display disturbance occurs Calculation for the next frame is started immediately aft...

Page 497: ...18 139 MB86R02 Jade D Hardware Manual V1 64 VSYNC is output 1 dot clock faster than HSYNC ...

Page 498: ...ters VSYNC HSYNC VDP 1 rasters VSP 1 rasters Assert Vsync Interrupt Assert Vsync Interrupt Assert Frame Interrupt Ri Gi Bi Ri Gi Bi Interlace Video Timing In the above diagram VTR HDP etc are the setting values of their associated registers The interlace mode also operates at the same timing as the interlace video mode The only difference between the two modes is the output image data ...

Page 499: ...register is 1 the equalizing pulse is inserted into the CSYNC signal producing the waveform shown below Fig 11 13 Composite Synchronous Signal with Equalizing Pulse The equalizing pulse is inserted when the vertical blanking time period starts It is also inserted three times after the vertical synchronization time period has elapsed CSYNC VSYNC CSYNC VSYNC odd field even field odd field even field...

Page 500: ... integer 32bit fixed point integer or 32bit floating point There is a limitation by itself And algorithm also has limitation Not all possible parameter or data can proceed correctly Object coordinates OC Clip coordinates CC Normalized device coordinates NDC Drawing device coordinates DC MVP Transformation Clipping 3D 2D Transformation View port transformation Back face culling ...

Page 501: ...nate transformation is processed as Zoc 0 When GMDR0 0 is 0 orthogonal projection transformation OC CC coordinate transformation is processed as Wcc 1 0 Work only for C 0 Z 0 and ST 0 XY only vertex mode OC Object Coordinates CC Clip Coordinates Ma0 to Md3 OC CC Matrix Xoc to Zoc X Y and Z of OC coordinate system Xcc to Woc X Y Z and W of CC coordinate system 18 9 1 3 3D 2D transformation CC NDC c...

Page 502: ...Note Xmin Xmax Ymin Ymax Zmin Zmax and Wmin are the clip boundary values set by the G_ViewVolumeXYClip ZClip WClip packet Clipping on off View volume clipping on off can be switched by using the clip boundary values set by the G_ViewVolumeXYClip Zclip WClip packet To switch view volume clipping to off set the maximum and minimum values of the geometry data format IEEE single precision floating poi...

Page 503: ...2 pixels or more 1 XY on the view volume clip frame of the CC coordinate system may be drawn one pixel outside or inside the frame due to an operation error when it is finally mapped to the DC coordinate system 2 When the end point of a line overlaps the view volume frame mapped to the DC coordinate system there are two cases where the dots on the frame are drawn and not drawn depending on the spe...

Page 504: ...ed and a mode in which drawing for the back face is inhibited back face culling is supported The on off operation is controlled by the GMDR2 0 setting GMDR2 0 must be set to 1 only when back face carling is required When back face culling is not required such as in line point and polygon primitive GMDR2 0 must be set to 0 ...

Page 505: ...nt format The data format to use is selected by setting the GMDR0 register 1 32 bit single precision floating point format 31 30 23 22 0 s e f s Sign bit 1 bit e Exponent part 8 bits f Mantissa 23 bits 1 f shows the fraction 1 is a hidden bit The numerical value of the floating point format becomes 1 s 1 f 2 e 127 0 e 255 2 Signed fixed point format SFIX16 16 31 30 16 15 0 s Int Frac s Sign bit 1 ...

Page 506: ... output command Log output of drawing coordinates device coordinates can be performed concurrently with nclip_Points int primitive drawing Log output can be controlled using the command with log output on off attribute log output is performed only when the log output on attribute is specified Log output dedicated command When the log output dedicated command is used log output of the device coordi...

Page 507: ...e top left as shown in the figure below The maximum coordinates is 4096 4096 Each drawing frame is located in the Graphics Memory by setting the address of the origin and resolution of X direction size Although the size of Y direction does not need to be set Y coordinates which are max at drawing must not be overlapped with other area In addition at drawing specifying the clip frame top left and b...

Page 508: ... T coordinates exceed the maximum pattern size the repeat cramp or border color option is selected 18 10 1 3 Frame buffer For drawing the following area must be assigned to the Graphics Memory The frame size count of pixels on X direction is common for these areas Drawing frame The results of drawing are stored in the graphical image data area Both the direct and indirect color mode are applicable...

Page 509: ...t Line Triangle High speed 2DLine High speed 2DTriangle Polygon 18 10 2 2 Polygon drawing function An irregular polygon including concave shape is drawn by hardware in the following manner 1 Execute PolygonBegin command Initialize polygon drawing hardware 2 Draw vertices Draw outline of polygon and plot all vertices to polygon draw flag buffer using high speed 2DTriangle primitive 3 Execute Polygo...

Page 510: ...elationship between coordinates Xs XUs and XLs For example in the above diagram when a right hand triangle is drawn using the parameter that shows the coordinates positional relationship Xs upper edge start Y coordinates XUs or Xs lower edge start Y coordinates XLs the appropriate picture may not be drawn V0 Upper edge Long edge V1 Lower edge V2 Upper triangle Lower triangle V1 V0 V2 Upper edge Lo...

Page 511: ...e direction dZdy Z DDA value of long edge direction dRdy R DDA value of long edge direction dGdy G DDA value of long edge direction dBdy B DDA value of long edge direction dSdy S DDA value of long edge direction dTdy T DDA value of long edge direction dQdy Q DDA value of long edge direction USN Count of spans of upper triangle LSN Count of spans of lower triangle dZdx Z DDA value of horizontal dir...

Page 512: ... enables a drawing of a specific pixel with transmission If part of the source and destination of the BLT field are physically overlapped in the display frame the start address from which vertex the BLT field to be transferred must be set correctly 18 10 3 2 Pattern data format MB86R02 Jade D can handle three bit map data formats indirect color mode 8 bits pixel direct color mode 16 bits pixel and...

Page 513: ...ted pixel position of the polygon For the S and T coordinates the selectable texture data size is any value in the range from 4 to 4096 pixels represented as an exponent of 2 18 10 4 2 Texture color Drawing of 8 16 bit direct color is supported for the texture pattern For drawing 8 bit direct color only point sampling can be specified for texture interpolation only decal can be specified for the b...

Page 514: ... the upper bits of the applied S T coordinates When the texture pattern size is 64 64 pixels the lower 6 bits of the integer part of S T coordinates are used for S and T coordinates Cramp When the applied S T coordinates is either negative or larger than the specified texture pattern size cramp the S T coordinate as follows instead of texture S 0 S 0 S Texture X size 1 S Texture X size 1 Border Wh...

Page 515: ...pective correction This function corrects the distortion of the 3D perspective in the texture mapping For this correction the Q component of the texture coordinates Q 1 W is set based on the W component of 3D coordinates of the vertex When the texture coordinates are large values the texture may not be drawn correctly when perspective correction is performed This phenomenon occurs due to the preci...

Page 516: ...CO C0 CT CP Stencil This mode selects the display color from the texture color with MSB as a flag MSB 1 Texture color MSB 0 Polygon color 18 10 4 7 Bi linear high speed mode Bi linear filtering is performed at high speed by creating normal texture data in advance with four pixel redundancy for one pixel One pixel requires information of about four pixels so an area of four times the normal area is...

Page 517: ...8 57 58 59 60 61 62 63 56 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 00 01 08 09 01 02 09 10 08 09 16 17 12 13 14 15 16 17 24 25 17 18 25 26 24 25 32 33 25 26 33 34 32 33 40 41 33 34 41 42 40 48 49 41 42 49 50 41 49 56 57 49 50 57 58 48 57 00 01 57 58 01 02 56 0 1 to 6 7 0 1 2 3 4 5 6 7 06 07 14 15 07 00 15 08 09 10 17 18 23 16 15 08 to 30 31 22 23 31 24 23 16 to 38 39 30 31 39 32 31 24 to 54 55 46 47 to 38 ...

Page 518: ... operation drawing It can be used only when the direct color mode 16 bits pixel is used The blended color C is calculated as shown below when the color of the pixel to be drawn is CP the color of frame buffer is CF and the alpha value is A C CP A 1 A CF The alpha value is specified as 8 bit data 00h means alpha value 0 and FFh means alpha value 100 When the texture mapping function is enabled the ...

Page 519: ...nt This function compares the Z value of a new pixel to be drawn and the existing Z value in the Z buffer Display not display is switched according to the Z compare mode setting Define the Z buffer access options in the ZWRITEMASK mode The Z compare operation type is determined by the Z compare mode Either 16 or 8 bits can be selected for the Z value ZWRITEMASK 1 Compare Z values no Z value write ...

Page 520: ...angle Drawing Attributes Drawing Attribute Description Shading Gouraud shading or flat shading selectable In case of indirect color mode gray scale gouraud shading is possible Alpha blending Set alpha blending enable disable per polygon Alpha blending coefficient Set color blending ratio of alpha blending How to set gray scale gouraud shading 1 Set Frustum bit of GMDR0 register to 0 2 Set identity...

Page 521: ...r texture mapping or tiling Texture filter Select either point sampling or bi linear filtering Texture coordinates correction Select either linear or perspective correction Texture wrap Select either repeat or cramp of texture pattern Texture blend mode Select either decal or modulate Bi linear high speed mode Texture data is created in a dedicated format to perform high speed bi linear filtering ...

Page 522: ...n enlarge shrink Vertical and Horizontal 2 Horizontal 2 Vertical and Horizontal 1 2 Horizontal 1 2 Character pattern color Set character color and background color Transparency non transparency Set background color to transparency non transparency 18 10 7 Bold Line 18 10 7 1 Starting and ending points In the CREMSON bold line mode the starting and ending points are vertical to the principal axis I...

Page 523: ...ing the CORAL broken line pattern In the CORAL bold line mode only the CORAL broken line pattern is supported Interpolation of broken line pattern Two types of interpolation modes are supported No interpolation mode Interpolation is not performed Broken line pattern reference address fix mode The same broken line pattern is referenced for several pixels before and after the joint of the bold line ...

Page 524: ...nection of the overlaid part of the edging line For example when the line body depth information and edging section depth information are the same the drawing result of the edging line is like the intersection shown in the figure below Also when the line body depth information and edging section depth information are different the drawing result of the edging line is like the solid intersection sh...

Page 525: ...ng a triangle as shown in the figure below The edging line joint is also interpolated using a triangle but the said depth information makes it possible to represent a good connection as shown in the figure below Only LineStrip primitive can interpolate and clipping sometimes breaks LineStrip Caution Sometime joint shape looks not perfect using approximate calculation ...

Page 526: ...line shadowing One is a shadow line and another is a shadow composition line A shadow composition line is used for avoiding an overlap with body line And drawing priority can be set for rendering performance or anti aliasing Triangle and polygon A shadow primitive are drawn in a triangle and polygon shadowing Drawing priority is fixed as a body primitive is first Body line Shadow line Shadow compo...

Page 527: ...FO by one of the following methods Write to display FIFO by CPU Transfer from main memory to display FIFO by external DMA Transfer from graphics memory to display FIFO by register setting Display list Command 1 Data 1 1 Data 1 2 Data 1 3 Display list Command 2 Data 2 1 Data 2 2 Data 2 3 Display List ...

Page 528: ...to display list command Vertex Number Specified in Vertex Code Vertex Vertex number Line Vertex number Triangle 00 V0 V0 01 V1 V1 10 Setting prohibited V2 11 Setting prohibited Setting prohibited 18 11 1 2 Parameter format The parameter format of the geometry command depends on the value set in the D field of GMDR0 When the D field is 00 all parameters are handled in the floating point format When...

Page 529: ... G_Viewport Scale to screen coordinates X Y and set origin offset G_DepthRange Scale to screen coordinates Z and set origin offset G_LoadMatirix Load geometric transformation matrix G_ViewVolumeXYClip Set boundary value X Y of view volume clip G_ViewVolumeZClip Set boundary value Z of view volume clip G_ViewVolumeWClip Set boundary value W of view volume clip OverlapXYOfft See Command table Sets X...

Page 530: ...100_0000 G_Viewport 0100_0001 G_DepthRange 0100_0010 G_LoadMatirix 0100_0011 G_ViewVolumeXYClip 0100_0100 G_ViewVolumeZClip 0100_0101 G_ViewVolumeWClip 0100_0110 SetLVertex2i 0111_0010 SetLVertex2iP 0111_0011 SetModeRegister 1100_0000 SetGModeRegister 1100_0001 OverlapXY0fft 1100_1000 OverlapZ0fft 1100_1001 DC_LogOutAddr 1100_1100 SetColorRegister 1100_1110 G_BeginE 1110_0001 G_EndE 1110_0011 ...

Page 531: ...s float 0001_0101 Line_Strip int Line_Strip int 0001_0111 Triangle_Strip int Triangle_Strip float 0001_1000 Triangle_Fan int Triangle_Fan float 2 Unclipped integer setup type for G_Begin This command does not clip the view volume Only XY is enabled as the input parameter In setup processing XY is calculated in the integer format int The screen projection GMDR0 0 1 performed using this command is n...

Page 532: ...le_Fan int Triangle_Fan int 4 Unclipped integer setup type for G_BeginE This command does not clip the view volume Only XY is enabled as the input parameter In setup processing XY is calculated in the integer format The screen projection GMDR0 0 1 performed using this command is not assured GMDR0 FX has no mean for G_BeginE Code Command GMDR0 FX 0 Command GMDR0 FX 1 0011_0000 nclip_Points int ncli...

Page 533: ...rved No operation G_Init Format 1 31 24 23 16 15 0 G_Init Reserved Reserved The G_Init command initializes geometry engine Execute this command before processing G_End Format 1 31 24 23 16 15 0 G_End Reserved Reserved The G_End command ends one primitive The G_Vertex command must be specified between the G_Begin command and G_End command ...

Page 534: ...egin and G_End Command Points Handles primitive as point Lines Handles primitive as independent line Polygon Handles primitive as polygon Triangles Handles primitive as independent triangle Line_Strip Handles primitive as line strip Triangle_Strip Handles primitive as triangle strip Triangle_Fan Handles primitive as triangle fan Usable combinations of GMDR0 mode setting and primitives are as follo...

Page 535: ...ColorRegister XY only vertex or OverLapZofft can placed between G_BeginE and G_EndE Command Points Handles primitive as point Lines Handles primitive as independent line Interpolation of the joint and broken line pattern is not supported Polygon Handles primitive as polygon Triangles Handles primitive as independent triangle Line_Strip Handles primitive as line strip Triangle_Strip Handles primiti...

Page 536: ...ZC bit of MDR1 or MDR2 1 the Z bit of the GMDR0 register must be set to 1 When Gouraud shading is performed SM bit of MDR2 1 the C bit of the GMDR0 register must be set to 1 When texture mapping is performed TT bits of MDR2 10 the ST bit of the GMDR0 register must be set to 1 When the Z bit of the GMDR0 register is 0 input Z Zoc is treated as 0 Use values normalized to 0 and 1 as texture coordinat...

Page 537: ...ed The G_DepthRange command sets the Z scale offset value used when an NDC is transformed into a DC G_LoadMatrix Format 1 31 24 23 16 15 0 G_LoadMatrix Reserved Reserved Matrix_a0 float fixed Matrix_a1 float fixed Matrix_a2 float fixed Matrix_a3 float fixed Matrix_b0 float fixed Matrix_b1 float fixed Matrix_b2 float fixed Matrix_b3 float fixed Matrix_c0 float fixed Matrix_c1 float fixed Matrix_c2 ...

Page 538: ...ry value in view volume clipping G_ViewVolumeZClip Format 1 31 24 23 16 15 0 G_ViewVolumeZClip Reserved Reserved ZMIN float fixed ZMAX float fixed The G_ViewVolumeZClip command sets the Z coordinates of the clip boundary value in view volume clipping G_ViewVolumeWClip Format 1 31 24 23 16 15 0 G_ViewVolumeWClip Reserved Reserved WMIN float fixed The G_ViewVolumeWClip command sets the W coordinates...

Page 539: ...ommand sets the Z offset of the shade primitive relative to the body primitive sets the Z offset of the edge primitive relative to the body primitive and sets the Z offset of the interpolation primitive relative to the body primitive with the top left rule non applicable in effect At this time the following relationship must be satisfied when for example GREATER is specified for the Z value compar...

Page 540: ... Command Code Explanation MDR1 0000_0000 MDR1 command sets MDR1 for the body primitive MDR1S 0000_0010 MDR1S command sets MDR1 for the shade primitive MDR1B 0000_0100 MDR1B command sets MDR1 for the edge primitive MDR2 0000_0001 MDR2 command sets MDR2 for the body primitive MDR2S 0000_0011 MDR2S command sets MDR2 for the shade primitive MDR2LT 0000_0111 MDR2LT command sets MDR2 for the top left no...

Page 541: ...0_0100 ForeColorBorder command sets the foreground color for the edge primitive BackColorBorder 0000_0101 BackColorBorder command sets the background color for the edge primitive SetRegister Format 2 31 24 23 16 15 0 SetRegister Count Address Val 0 Val 1 Val n The SetRegister command is upper compatible with CREMSON SetRegister It can specify the address of a register in the geometry engine SetLVe...

Page 542: ...ias option principal axis Y DrawLine2i DrawLine2iP ZeroVector Draws high speed 2DLine with vertex 0 as starting point OneVector Draws high speed 2DLine with vertex 1 as starting point DrawTrap TrapRight Draws right triangle TrapLeft Draws left triangle DrawVertex2i DrawVertex2iP TriangleFan Draws high speed 2DTriangle FlagTriangleFan Draws high speed 2DTriangle for multiple vertices random shape D...

Page 543: ...18 185 MB86R02 Jade D Hardware Manual V1 64 BltCopyAlt AlphaBlendP Alpha blending is supported see the alpha map BltCopyAlternateP ...

Page 544: ..._0100 DrawTrap 0000_0101 DrawVertex2i 0000_0110 DrawVertex2iP 0000_0111 DrawRectP 0000_1001 DrawBitmapP 0000_1011 BltCopyP 0000_1101 BltCopyAlternateP 0000_1111 LoadTextureP 0001_0001 BltTextureP 0001_0011 BltCopyAltAlphaBlendP 0001_1111 SetVertex2i 0111_0000 SetVertex2iP 0111_0001 Draw 1111_0000 SetRegister 1111_0001 Sync 1111_1100 Interrupt 1111_1101 Nop 1111_1111 ...

Page 545: ..._01011 AntiXvectorBlpClear 001_01100 AntiYvectorBlpClear 001_01101 AntiXvectorNoEndBlpClear 001_01110 AntiYvectorNoEndBlpClear 001_01111 ZeroVector 001_10000 Onevector 001_10001 ZeroVectorNoEnd 001_10010 OnevectorNoEnd 001_10011 ZeroVectorBlpClear 001_10100 OnevectorBlpClear 001_10101 ZeroVectorNoEndBlpClear 001_10110 OnevectorNoEndBlpClear 001_10111 AntiZeroVector 001_11000 AntiOnevector 001_1100...

Page 546: ...1 TopLeft 010_00100 TopRight 010_00101 BottomLeft 010_00110 BottomRight 010_00111 LoadTexture 010_01000 LoadTILE 010_01001 TrapRight 011_00000 TrapLeft 011_00001 TriangleFan 011_00010 FlagTriangleFan 011_00011 Flush_FB 110_00001 Flush_Z 110_00010 PolygonBegin 111_00000 PolygonEnd 111_00001 ClearPolyFlag 111_00010 Normal 111_11111 ...

Page 547: ...No operation Interrupt Format1 31 24 23 16 15 0 Interrupt Reserved Reserved The Interrupt command generates interrupt request to host CPU Sync Format9 31 24 23 16 15 4 0 Sleep Reserved Reserved flag The Sync command suspends all subsequent display list processing until event set in flag detected Flag Bit number 4 3 2 1 0 Bit field name Reserved Reserved Reserved Reserved VBLANK Bit 0 VBLANK VBLANK...

Page 548: ...egisters Commands Normal Sets vertex data X Y PolygonBegin Starts calculation of circumscribed rectangle for random shape to be drawn Calculate vertices of rectangle including all vertices of random shape defined between PolygonBegin and PolygonEnd Flag Not used SetVertex2iP Format8 31 24 23 16 15 4 3 2 1 0 SetVertex2i Command Reserved flag vertex Ydc Xdc The SetVertex2iP command sets vertices dat...

Page 549: ...ommand Flush_FB Flushes drawing data in the drawing pipeline into the graphics memory Place this command at the end of the display list Flush_Z Flushes Z value data in the drawing pipeline into the graphics memory When using the Z buffer place this command together with the Flush_FB command at the end of the display list DrawPixel Format5 31 24 23 16 15 0 DeawPixel Command Reserved PXs PYs The Dra...

Page 550: ...position cleared YvectorNoEndBlpClear Draws line principal axis Y without end point drawing and prior to drawing broken line pattern reference position cleared AntiXvector Draws anti alias line principal axis X AntiYvector Draws anti alias line principal axis Y AntiXvectorNoEnd Draws anti alias line principal axis X and without end point drawing AntiYvectorNoEnd Draws anti alias line principal axi...

Page 551: ...e pattern reference position cleared OneVectorNoEndBlpClear Draws line from vertex 1 to vertex 0 principal axis Y without end point drawing and prior to drawing broken line pattern reference position cleared AntiZeroVector Draws anti alias line from vertex 0 to vertex 1 AntiOneVector Draws anti alias line from vertex 1 to vertex 0 AntiZeroVectorNoEnd Draws anti alias line from vertex 0 to vertex 1...

Page 552: ...ne pattern reference position cleared OneVectorNoEndBlpClear Draws line from vertex 1 to vertex 0 principal axis Y without end point drawing and prior to drawing broken line pattern reference position cleared AntiZeroVector Draws anti alias line from vertex 0 to vertex 1 AntiOneVector Draws anti alias line from vertex 1 to vertex 0 AntiZeroVectorNoEnd Draws anti alias line from vertex 0 to vertex ...

Page 553: ... draws high speed 2DTriangle It starts triangle drawing after setting parameters at 2DTriangle Drawing registers Commands TriangleFan Draws high speed 2DTriangle FlagTriangleFan Draws high speed 2DTriangle for polygon drawing in the flag buffer DrawVertex2iP Format7 31 24 23 16 15 0 DrawVertex2iP Command Reserved vertex Ydc Xdc The DrawVertex2iP command draws high speed 2DTriangle It starts drawin...

Page 554: ...Pattern 1 Pattern n The DrawBitmapP command draws rectangle patterns Please set XRES X resolution to in 8 byte units when using this command Commands BltDraw Draws rectangle of 8 bits pixel or 16 bits pixel DrawBitmap Draws binary bitmap character pattern Bit 0 is drawn in transparent or background color and bit 1 is drawn in foreground color The RsizeX has to be up to 2016 in this command DrawBit...

Page 555: ...right coordinates BltCopyAlternateP Format5 31 24 23 16 15 0 BltCopyAlternateP Command Reserved SADDR SStride SRYs SRXs DADDR DStride DRYs DRXs BRsizeY BRsizeX The BltCopyAlternateP command copies rectangle between two separate drawing frames Please set XRES X resolution to in 8 byte units when using this command And please set SStride and DStride to in 8 byte units The actual address of a source ...

Page 556: ... alpha map specified using ABR alpha base address BlendStride BlendRXs BlendRYs and then copies the result of the alpha blending to the destination specified using FBR frame buffer base address XRES X resolution DRXs and DRYs Please set XRES X resolution to in 8 byte units when using this command And please set SStride and BlendStride to in 8 byte units The actual address of a source address for V...

Page 557: ...11 10 9 8 7 6 5 4 3 2 1 0 000 000 Ys S S S S Int Frac 004 001 Xs S S S S Int Frac 008 002 dXdy S S S S Int Frac 00C 003 XUs S S S S Int Frac 010 004 dXUdy S S S S Int Frac 014 005 XLs S S S S Int Frac 018 006 dXLdy S S S S Int Frac 01C 007 USN 0 0 0 0 Int 0 020 008 LSN 0 0 0 0 Int 0 040 010 Rs 0 0 0 0 0 0 0 0 Int Frac 044 011 dRdx S S S S S S S S Int Frac 048 012 dRdy S S S S S S S S Int Frac 04C ...

Page 558: ...18 200 MB86R02 Jade D Hardware Manual V1 64 017 S S S S S S S S Int Frac 060 018 dBdy S S S S S S S S Int Frac ...

Page 559: ... Frac 0C8 032 dSdy S S S Int Frac 0CC 033 Ts S S S Int Frac 0D0 034 dTdx S S S Int Frac 0D4 035 dTdy S S S Int Frac 0D8 036 Qs 0 0 0 0 0 0 0 INT Frac 0DC 037 dQdx S S S S S S S INT Frac 0E0 038 dQdy S S S S S S S INT Frac 140 050 LPN 0 0 0 0 Int 0 144 051 LXs S S S S Int Frac 148 052 LXde S S S S S S S S S S S S S S S Int Frac 14C 053 LYs S S S S Int Frac 150 054 LYde S S S S S S S S S S S S S S S...

Page 560: ... S S S Int 0 204 081 RYs S S S S Int 0 208 082 RsizeX S S S S Int 0 20C 083 RsizeY S S S S Int 0 240 090 SADDR 0 0 0 0 0 0 0 Address 244 091 SStride 0 0 0 0 Int 0 248 092 SRXs 0 0 0 0 Int 0 24C 093 SRYs 0 0 0 0 Int 0 250 094 DADDR 0 0 0 0 0 0 0 Address 254 095 DStride 0 0 0 0 Int 0 258 096 DRXs 0 0 0 0 Int 0 25C 097 DRYs 0 0 0 0 Int 0 260 098 BRsizeX 0 0 0 0 Int 0 264 099 BRsizeY 0 0 0 0 Int 0 268...

Page 561: ... CE FCNT NF FF FE SS DS PS 404 IFSR FD FE CE 408 IFCNT FCNT 40C SST SS 410 DS DS 414 PST PS 418 EST FD PE CE 420 108 MDR0 FS ZP CF CY CX BSV BSH 424 109 MDR1 MDR1S MDR1B MDR1TL LW BP BL LOG BM ZW ZCL ZC AS SM 428 10a MDR2 MDR2S MDR2TL TT LOG BM ZW ZCL ZC AS SM 42C 10b MDR3 BA TAB TBL TWS TWT TF TC 430 10c MDR4 LOG BM TE 43C 10f MDR7 LTH EZ GG PGH PTH PZH ...

Page 562: ...E 444 111 XRES XRES 448 112 ZBR ZBASE 44C 113 TBR TBASE 450 114 PFBR PFBASE 454 115 CXMIN CLIPXMIN 458 116 CXMAX CLIPXMAX 45C 117 CYMIN CLIPYMIN 460 118 CYMAX CLIPYMAX 464 119 TXS TXSN TXSM 468 11a TIS TISN TISM 46C 11b TOA XBO 470 11C SHO SHOFFS 474 11D ABR ABASE 480 120 FC FGC8 16 24 484 121 BC BGC8 16 24 488 122 ALF A 48C 123 BLP 494 129 TBC BC16 24 ...

Page 563: ... 13 12 11 10 9 8 7 6 5 4 3 2 1 0 540 150 LX0dc 0 0 0 0 Int 0 544 151 LY0dc 0 0 0 0 Int 0 548 150 LX1dc 0 0 0 0 Int 0 54C 151 LY1dc 0 0 0 0 Int 0 580 160 X0dc 0 0 0 0 Int 0 584 161 Y0dc 0 0 0 0 Int 0 588 162 X1dc 0 0 0 0 Int 0 58C 163 Y1dc 0 0 0 0 Int 0 590 164 X2dc 0 0 0 0 Int 0 594 165 Y2dc 0 0 0 0 Int 0 ...

Page 564: ...dress used by the SetRegister command BaseAddress GeometryBase 0xF1FF_8000 Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 000 GCTR FO FCNT NF FF FE GS SS PS 040 2010 GMDR0 FX CF DF ST Z C F 044 2011 GMDR1 BO EP AA GMDR1E PO LV TC BC UW BM TM BP SP BO EP AA 048 2012 GMDR2 FD CF GMDR2E TL SP FD CF 400 DFIFOG ...

Page 565: ...ts 24 to 22 are not cleared until 0 is set Bit 1 and 0 PS Pixel engine Status Indicate status of pixel engine unit 00 Idle 01 Busy 10 Reserved 11 Reserved Bit 5 and 4 DS DDA Status Indicate status of DDA 00 Idle 01 Busy 10 Busy 11 Reserved Bit 9 and 8 SS Setup Status Indicate status of Setup unit 00 Idle 01 Busy 10 Reserved 11 Reserved Bit 12 FE FIFO Empty Indicates whether data contained or not i...

Page 566: ...er Indicates count of empty entries of display list FIFO 0 to 100000H Bit 22 CE Display List Command Error Indicates command error occurrence Not all error can detect Requires software reset or hardware reset for recovery 0 Normal 1 Command error detected Bit 24 FO FIFO Overflow Indicates FIFO overflow occurrence 0 Normal 1 FIFO overflow detected ...

Page 567: ...14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name SS R W R Initial value 00 This is a miller register for bits 9 to 8 of the CTR register DST DDA Status Register address DrawBaseAddress 410H Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name DS R W RW Initial value 00 This is a mirror register for bits 5 to 4 of the CTR register PST Pixe...

Page 568: ...0 00 0 0 00 00 Bit 1 to 0 BSH Bitmap Scale Horizontal Sets horizontal zoom ratio of bitmap draw 00 x1 01 x2 10 x1 2 01 Reserved Bit 3 to 2 BSV Bitmap Scale Vertical Sets vertical zoom ratio of bitmap draw 00 x1 01 x2 10 x1 2 01 Reserved Bit 8 CX Clip X enable Sets X coordinates clipping mode 0 Disabled 1 Enabled Bit 9 CY Clip Y enable Sets Y coordinates clipping mode 0 Disabled 1 Enabled Bit 16 an...

Page 569: ...18 211 MB86R02 Jade D Hardware Manual V1 64 Bit30 29 FS Frame Select for Sync rendering command 00 FRAME0 initial value Synchronize with FRAME0 01 FRAME1 Synchronize with FRAME1 10 RESERVED 11 RESERVED ...

Page 570: ...a drawing that involves the shade primitive the edge primitive or the top left non applicable primitive is the value set for MDR1 Please set ZC bit bit 2 to 0 when draw BltCopyAltAlphaBlendP command Bit 1 AS Alpha Shading mode Sets the shading mode for alpha 0 Alpha flat shading 1 Alpha Gouraud shading Bit 2 ZC Z Compare mode Sets Z comparison mode 0 Disabled 1 Enabled Bit 5 to 3 ZCL Z Compare Log...

Page 571: ...101 NOP 0110 XOR 0111 OR 1000 NOR 1001 EQUIV 1010 INVERT 1011 OR REVERSE 1100 COPY INVERTED 1101 OR INVERTED 1110 NAND 1111 SET Bit 19 BL Broken Line Selects line type 0 Solid line 1 Broken line Bit 20 BP Broken line Period Selects broken line cycle 0 32 bits 1 24 bits Bit 28 to 24 LW Line Width Sets line width for drawing line 00000 1 pixel 00001 2 pixels 11111 32 pixels ...

Page 572: ...ft non applicable primitive The value after a drawing that involves the shade primitive or the top left non applicable primitive is the value set for MDR2 Must set SM AS TT 0 for MDR2S Bit 0 SM Shading Mode Sets shading mode 0 Flat shading 1 Gouraud shading Bit 1 AS Alpha Shading mode Sets alpha shading mode This mode is enabled for only alpha 0 Alpha flat shading 1 Alpha gouraud shading Bit 2 ZC ...

Page 573: ... 9 LOG Logical operation Sets type of logic operation 0000 CLEAR 0001 AND 0010 AND REVERSE 0011 COPY 0100 AND INVERTED 0101 NOP 0110 XOR 0111 OR 1000 NOR 1001 EQUIV 1010 INVERT 1011 OR REVERSE 1100 COPY INVERTED 1101 OR INVERTED 1110 NAND 1111 SET Bit 29 to 28 TT Texture Tile Select Selects texture or tile pattern 00 Neither used 01 Enabled tiling 10 Enabled texture 11 Reserved ...

Page 574: ...rrect Sets texture coordinates correction mode 0 Disabled 1 Enabled Bit 5 TF Texture Filtering Sets type of texture interpolation filtering 0 Point sampling 1 Bi linear filtering Bit 9 and 8 TWT Texture Wrap T Sets type of texture coordinates T direction wrapping 00 Cramp 01 Repeat 10 Border 11 Reserved Bit 11 and 10 TWS Texture Wrap S Sets type of texture coordinates S direction wrapping 00 Cramp...

Page 575: ...t is not set to the alpha blending mode the stencil mode and stencil alpha mode perform the same function as the normal mode 00 Normal 01 Stencil 10 Stencil alpha 11 Reserved Bit 24 BA Bilinear Accelerate Mode Improves the performance of bi linear filtering although a texture area of four times the default texture area is used 0 Default texture area used 1 Texture area four times default texture a...

Page 576: ...ansparent mode 0 Not perform transparent processing 1 Not draw pixels that corresponds to set transparent color in BLT transparancy copy Note Set the blend mode BM to normal Bit 8 to 7 BM Blend Mode Sets blend mode 00 Normal source copy 01 Reserved 10 Drawing with logic operation 11 Reserved Bit 12 to 9 LOG Logical operation Sets logic operation 0000 CLEAR 0001 AND 0010 AND REVERSE 0011 COPY 0100 ...

Page 577: ...ster is able to use only in 8 bit pixel mode Bit 4 GG Gray scale Gouraud Shading Sets gray scale gouraud shading mode 0 Hard mask on compatible Orchid 1 Hard mask off extension mode Note This register is used for gray scale gouraud shading This register is changed by internal processing Please don t set these bits except GG bit In case of gray scale gouraud shading drawing please set this register...

Page 578: ...444H Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name XRES R W RW Initial value Don t care This register sets the drawing frame horizontal resolution ZBR Z buffer Base Register address DrawBaseAddress 448H Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name ZBASE R W RW R0 Ini...

Page 579: ...ster sets the clip frame minimum X position CXMAX Clip X maximum Register address DrawBaseAddress 458H Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name CLIPXMAX R W RW Initial value Don t care This register sets the clip frame maximum X position CYMIN Clip Y minimum Register address DrawBaseAddress 45CH Bit number 31 30 29 28 27 26 25 ...

Page 580: ..._0000_0000 M 512 0_0000_0000_1000 M 8 0_0100_0000_0000 M 1024 0_0000_0001_0000 M 16 0_1000_0000_0000 M 2048 0_0000_0010_0000 M 32 1_0000_0000_0000 M 4096 0_0000_0100_0000 M 64 0_0000_1000_0000 M 128 0_0001_0000_0000 M 256 Other than the above Setting disabled Bit 28 to 16 TXSN Texture Size N Sets vertical texture size Any power of 2 between 4 and 4096 can be used Values that are not a power of 2 c...

Page 581: ...4 Other than the above Setting disabled Bit 22 to 16 TISN Title Size N Sets vertical tile size Any power of 2 between 4 and 64 can be used Values that are not a power of 2 cannot be used 0000100 N 4 0001000 N 8 0010000 N 16 0100000 N 32 1000000 N 64 Other than the above Setting disabled TOA Texture Buffer Offset address Register address DrawBaseAddress 46CH Bit number 31 30 29 28 27 26 25 24 23 22...

Page 582: ...t body drawing this offset address is set to 0 at shadow drawing the offset address calculated from each offset value of the X coordinates and of the Y coordinates is set This register is hardware controlled ABR Alpha map Base Register address DrawBaseAddress 474H Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name ABASE R W RW R0 Initial...

Page 583: ...in the color set at this register 8 bit color mode Bit 7 to 0 FGC8 Foreground 8 bit Color Sets the indirect color for the foreground color index code Bit 31 to 8 These bits are not used 16 bit color mode Bit 15 to 0 FGC16 Foreground 16 bit Color This field sets the 16 bit direct color for the foreground Note that the handling of bit 15 is different from that in ORCHID Up to ORCHID bit 15 is 0 for ...

Page 584: ...ster allows the background color of be transparent no drawing 8 bit color mode Bit 7 to 0 BGC8 Background 8 bit Color Sets the indirect color for the background color index code Bit 14 to 8 Not used Bit 15 BT Background Transparency Sets the transparent mode for the background color 0 Background drawn using color set for BGC field 1 Background not drawn transparent Bit 31 to 16 Not used 16 bit col...

Page 585: ...are selected bits 31 to 8 of the BLP register are used TBC Texture Border Color Register address DrawBaseAddress 494H Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name BC8 16 R W RW Initial value 0 This register sets the border color for texture mapping 8 bit color mode Bit 7 to 0 BC8 Border Color Sets the 8 bit direct color for the tex...

Page 586: ...N 0020H 0 0 0 0 Int 0 Address Offset value from DrawBaseAddress S Sign bit or sign extension 0 Not used or 0 extension Int Integer or integer part of fixed point data Frac Fraction part of fixed point data Sets X Y coordinates for triangle drawing Ys Y coordinates start position of long edge Xs X coordinates start position of long edge corresponding to Ys dXdy X DDA value of long edge direction XU...

Page 587: ... value at Xs Ys Zs of long edge corresponding to Ys dRdx R DDA value of horizontal direction dRdy R DDA value of long edge Gs G value at Xs Ys Zs of long edge corresponding to Ys dGdx G DDA value of horizontal direction dGdy G DDA value of long edge Bs B value at Xs Ys Zs of long edge corresponding to Ys dBdx B DDA value of horizontal direction dBdy B DDA value of long edge As Alpha value at Xs Ys...

Page 588: ...sign extension 0 Not used or 0 extension Int Integer or integer part of fixed point data Frac Fraction part of fixed point data Sets texture coordinates parameters for triangle drawing Ss S texture coordinates Xs Ys Zs of long edge corresponding to Ys dSdx S DDA value of horizontal direction dSdy S DDA value of long edge direction Ts T texture coordinates Xs Ys Zs of long edge corresponding to Ys ...

Page 589: ...of fixed point data Frac Fraction part of fixed point data Sets coordinates parameters for line drawing LPN Pixel count of principal axis direction LXs X coordinates start position of draw line In principal axis X Integer value of X coordinates rounded off In principal axis Y X coordinates in form of fixed point data LXde Inclination data for X coordinates In principal axis X Increment or decremen...

Page 590: ...nates position PYdc Sets Y coordinates position PZdc Sets Z coordinates position 18 11 10 Rectangle drawing registers Each register is used by the drawing commands The registers cannot be accessed from the CPU or using the SetRegister command Register Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXs 0200H 0 0 0 0 Int 0 RYs 0204H 0 0 0 0 Int 0 RsizeX...

Page 591: ... 0 BRsizeX 0260H 0 0 0 0 Int 0 BRsizeY 0264H 0 0 0 0 Int 0 TColor 0280H 0 Color BLPO 3E0CH BCR Address Offset from DrawBaseAddress S Sign bit or sign extension 0 Not used or 0 extension Int Integer or integer part of fixed point data Frac Fraction part of fixed point data Sets parameters for Blt operations SADDR Sets start address of source rectangle area in byte address SStride Sets stride of sou...

Page 592: ...0540H 0 0 0 0 Int 0 LY0dc 0544H 0 0 0 0 Int 0 LX1dc 0548H 0 0 0 0 Int 0 LY1dc 054cH 0 0 0 0 Int 0 Address Offset from DrawBaseAddress S Sign bit or sign extension 0 Not used or 0 extension Int Integer or integer part of fixed point data Frac Fraction part of fixed point data Sets coordinates of line end points for High speed 2DLine drawing LX0dc Sets X coordinates of vertex V0 LY0dc Sets Y coordin...

Page 593: ... 0 X1dc 0588h 0 0 0 0 Int 0 Y1dc 058ch 0 0 0 0 Int 0 X2dc 0590h 0 0 0 0 Int 0 Y2dc 0594h 0 0 0 0 Int 0 Address Offset from DrawBaseAddress S Sign bit or sign extension 0 Not used or 0 extension Int Integer or integer part of fixed point data Frac Fraction part of fixed point data Sets coordinates of three vertices for High speed 2DTriangle drawing X0dc Sets X coordinates of vertex V0 Y0dc Sets Y c...

Page 594: ...at the flags and status information of the drawing section are reflected in CTR Bit 1 and 0 PS Pixel engine Status Indicates status of pixel engine unit 00 Idle 01 Processing 10 Reserved 11 Reserved Bit 5 and 4 SS geometry Setup engine Status Indicates status of geometry setup engine unit 00 Idle 01 Processing 10 Processing 11 Reserved Bit 9 and 8 GS Geometry engine Status Indicates status of geom...

Page 595: ...ace in display list FIFO DFIFOD 0 More than half of DFIFOD free 1 Less than half of DFIFOD free Bit 20 to 15 FCNT FIFO Counter Indicates count of free stages 0 to 011111B of display list FIFO DFIFOD Bit 24 FO FIFO Overflow Indicates whether FIFO overflow occurred 0 Normal 1 FIFO overflow ...

Page 596: ...and Enable Float Setup mode See Geometry command code table Work Only for G_Begin Triangle s _Strip _Fan 0 disable 1 enable Bit 7 CF Color Format Specifies color data format 0 Independent RGB format Packed RGB format 1 Reserved Bit 6 and 5 DF Data Format Specifies vertex coordinates data format 00 Specifies floating point format Only independent RGB format can be used as color data format 01 Speci...

Page 597: ... Z Z data enable Sets whether to use Z coordinates 0 Not use Z coordinates 1 Uses Z coordinates Bit 1 C Color data enable Sets whether to use vertex color 0 Not use vertex color 1 Uses vertex color Bit 0 F Frustum mode Sets projective transformation mode Work only for C 0 Z 0 and ST 0 XY only vertex mode 0 Orthogonal projection transformation mode 1 Perspective projection transformation mode ...

Page 598: ...ged the same bit of GMDR1E is also changed Bit 4 BO Broken line Offset Sets broken line reference position If you want clear initial vertex only SetRegister BLPO before G_Begin and Set 1 for this bit Cannot change GMDR1 within G_Begin G_End 0 Broken line reference position not cleared for all vertexes 1 Broken line reference position cleared for all vertexes Bit 2 EP End Point mode Sets end point ...

Page 599: ...on Control Sets the MB86R02 Jade D Line algorithm version 0 Version 1 0 for backward compatibility 1 Version 2 0 recommended Bit 20 TC Thick line Correct Sets the interpolation mode for the bold line joint 0 Interpolation of bold line joint not performed 1 Interpolation of bold line joint performed Bit 16 BC Broken line Correct Sets the interpolation mode for the dashed line pattern 0 Interpolatio...

Page 600: ...rawn 1 Shadow primitive drawn Bit 4 BO Broken line Offset Sets the reference position of the dashed line pattern If you want clear initial vertex only SetRegister BLPO before G_Begin E and Set 1 for this bit Cannot change GMDR1E within G_Begin E G_End E 0 Reference position of dashed line pattern cleared for all vertexes 1 Reference position of dashed line pattern not cleared for all vertexes Bit ...

Page 601: ... R W W W Initial value 0 0 This register sets the geometry processing mode when a triangle is drawn Drawing performed using commands in range from G_Begin to G_End Bit 2 FD Face Definition Sets the face definition 0 Face defined as state with vertexes arranged clockwise 1 Face defined as state with vertexes arranged counterclockwise Bit 0 CF Cull Face Sets the drawing mode of the back 0 Back drawn...

Page 602: ...rection Non top left part s pixel quality is less than body using approximate calculation Bit 10 TL Top Left rule mode Sets the drawing algorithm 0 Top left rule applied compatible with CREMSON 1 Top left rule not applied Bit 8 SP Shadow Primitive Sets the drawing mode for the shadow primitive 0 Shadow primitive not drawn 1 Shadow primitive drawn Bit 2 FD Face Definition Sets the face definition 0...

Page 603: ... DFIFOG Geometry Displaylist FIFO with Geometry Register address Geometry BaseAddress 400H Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name DFIFOG R W W Initial value Don t care FIFO registers for Display List transfer ...

Page 604: ...ers 18 11 17 1 Display List DMA contol register list BaseAddress HostBaseAddress 0xF1FC_0000 Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIFC 0008 LTS LTS DTS FIFC 0010 LSTA LSTA FIFC 0040 LSA LSA FIFC 0044 LCO LCO FIFC 0048 LREQ LREQ ...

Page 605: ...transfer Ongoing DisplayList transfer is suspended by setting LTS to 1 LSTA displayList transfer STAtus Register address HostBaseAddress 10H Bit number 7 6 5 4 3 2 1 0 Bit field name Reserved LSTA R W R0 R Initial value 0 0 This register indicates the DisplayList transfer status from Graphics Memory LSTA is set to 1 while DisplayList transfer is in progress This status is cleared to 0 when Display...

Page 606: ... 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved LCO R W R0 RW Initial value 0 Don t care This register sets the DisplayList transfer count Set the display list transfer count by the long word When 1h is set 1 word data is transferred When 0 is set it is considered to be the maximum count and 16M 16 777 216 words of data are transferred...

Page 607: ...interrupt status is cleared by writing 0 to this register Bit 0 CERR Command Error Flag Indicates drawing command execution error interrupt Bit 1 CEND Command END Indicates drawing command end interrupt Bit 2 VSYNC0 Vertical Sync of display 0 Indicates vertical interrupt synchronization Bit 3 FSYNC0 Frame Sync of display 0 Indicates frame synchronization interrupt Bit 4 SYNCERR0 Sync Error of disp...

Page 608: ...ture 0 Indicates video capture 0 interrupt Bit 11 CAP1 Capture 1 Indicates video capture 1 interrupt Bit 17 and 16 Reserved This field is provided for testing Normally the read value is 0 but note that it may be 1 when a drawing command error Bit 0 has occurred ...

Page 609: ...Vertical Sync of display 0 Interrupt Mask Masks vertical synchronization interrupt Bit 3 FSYNC0H Frame Sync of display 0 Interrupt Mask Masks frame synchronization interrupt Bit 4 SYNCERR0M Sync Error of display 0 Mask Masks external synchronization error interrupt Bit 5 REGUD0M Register update of display 0 Mask Masks register update interrupt Bit 6 VSYNC1M Vertical Sync of display 1 Interrupt Mas...

Page 610: ...x register address space Additionally the red colour channel can be used on all three colour lookup tables to translate index values to colours 19 1 2 Features The contents of the CLUT are generated i g by the function y x power k where k is dependant on the panel characteristics The CLUT is a part of the display output interface and must be initialized by the application software during the initi...

Page 611: ...MB86R02 Jade D Hardware Manual V1 64 19 2 19 1 3 Position of the CLUT A CLUT is integrated in both video processing pipelines as shown below Figure 19 2 Location of the CLUT in the GDC ...

Page 612: ...name Field name shows bit name of the register R W R W shows the read write attribute of each bit field R Read W Write W1C Writing a value of 1 clears the register Reset value Reset value indicates the value of each bit field immediately after reset 0 Initial value is 0 1 Initial value is 1 X Undefined Unused register fields are marked with a solid grey background Bit vectors are unsigned integers...

Page 613: ...b bypass disable 1b bypass enable 19 3Limitations A duplicate block RAM does not exist to avoid visible artifacts during the reconfiguration of the color block RAM when the video frame is active It is therefore strongly recommended to modify the CLUT content only during the vertical blanking period or by turning off the display during the reconfiguration Note also that the internal bypass function...

Page 614: ... STOP_I STOP_O Figure 20 1 DITH inputs outputs 20 1 1 Features The dither unit supports Bypass mode In bypass mode the input data will be passed to the output where the 2 LSB of the input data will be dropped Spatial dithering mode In spatial dithering mode the intensities of neighboring pixels are modified so that their combined intensities average out to the desired value Using a 4x4 matrix see ...

Page 615: ...n RGB888 monitor see table 1 1 2 dither_ Align dither_ format Output format 888 777 666 565 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 X 888 RGB 888 0 777 0 RGB 777 1 777 RGB 777 0 0 666 0 0 RGB 666 1 666 RGB 666 0 0 0 565 0 0 0 R5 0 0 G6 0 0 0 B5 1 565 R5 0 0 0 G6 0 0 B5 0 0 0 Table 1 1 2 Output format as a function of dither_align and dither_format 20 1 2 Position One dither unit is integrated in e...

Page 616: ...I VALID_O RGB_I RGB_O 00 00 01 00 00 00 10 00 Hcnt Vcnt 0 8 10 2 Dith_value Random Hsync Vsync 11 00 10 00 00 00 01 00 00 01 01 01 10 01 11 01 10 01 00 01 01 01 11 01 10 00 01 00 11 00 0 8 2 12 4 14 6 12 4 14 6 0 8 2 10 Figure 20 3 Timing diagram for spatial dithering mode ...

Page 617: ...Field name Field name shows bit name of the register R W R W shows the read write attribute of each bit field R Read W Write W1C Writing a value of 1 clears the register Reset value Reset value indicates the value of each bit field immediately after reset 0 Initial value is 0 1 Initial value is 1 X Undefined Unused register fields are marked with a solid grey background Bit vectors are unsigned in...

Page 618: ...her_mode Dithering Mode Register 0b temporal 1b spatial Bit 0 dither_bypass Bypass for Dither Unit 0b bypass disable 1b bypass enable 20 3 Limitations There is no shadow register for the synchronization of configuration parameters during the vertical blanking period To avoid visible artifacts during reconfiguration we recommend you to find a trigger point to modify the configuration register durin...

Page 619: ...e such signatures e g to determine whether the displayed image is exactly identical or almost identical to the original image data submitted This is necessary for critical safety displays and helps to fulfil the requirements of safety standards e g Automotive Safety Integrity Level ASIL 21 3 Feature List Generation of 2 different picture signatures for each color channel summation of color values ...

Page 620: ...load for the microcontroller 21 3 6 Self Restoring Error Counter A counter is incremented if one of the active signature results differs from the corresponding reference values If a programmable error counter threshold is reached an interrupt may be generated The same counter is reset to zero if a programmable number of consecutive video frames with correct signature values is received 21 3 7 Inte...

Page 621: ...er Description The register descriptions in the following sections use the format shown below to describe each bit field of a register Register address Offset Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field name R W Reset value Meaning of items and sign Register address Register address shows the address Offset address of the register Bit numb...

Page 622: ...ndow VerticalUpperLeft Base address 24H VerticalLowerRightW0 Evaluation Window VerticalLowerRight Base address 28H SignAReferenceRW0 Signature A Reference value channel R Base address 2CH SignAReferenceGW0 Signature A Reference value channel G Base address 30H SignAReferenceBW0 Signature A Reference value channel B Base address 34H SignBReferenceRW0 Signature B Reference value channel R Base addre...

Page 623: ...H Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field name SrcSel Vmask_mode Hmask_mode R W RW RW RW Reset value 0H 0H 0H SIG modul general config register Bit 17 16 SrcSel Source Select 00b source 0 01b source 1 10b source 2 11b source 3 Bit 9 8 Vmask_mode 00b nomask 01b mask inside vertical coordinates 10b mask outside vertical coordinates 11b r...

Page 624: ...on Window HorizontalUpperLeft Bit 11 0 HorizontalUpperLeftW0 Evaluation Window HorizontalUpperLeft Register content is overtaken with write of Register TriggerW0 Trigger HorizontalLowerRightW0 Register address BaseAddress 1CH Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field name HorizontalLowerRightW0 R W RW Reset value 0H Evaluation Window Hor...

Page 625: ... frame start SignAReferenceBW0 Register address BaseAddress 30H Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field name SignAReferenceBW0 R W RW Reset value 0H Signature A Reference value channel B Bit 31 0 SignAReferenceBW0 Signature A Reference value channel B Register content is overtaken with write of Register TriggerW0 Trigger during cyclic ...

Page 626: ...3 2 1 0 Field name ThrBGW0 R W RW Reset value 0H Threshold Signature B Bit 31 0 ThrBGW0 Threshold Signature B for channel G Register content is overtaken with write of Register TriggerW0 Trigger during cyclic mode with every frame start ThrBBW0 Register address BaseAddress 48H Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field name ThrBBW0 R W RW...

Page 627: ...n see the relevant status field InterruptStatusW0 Register address BaseAddress 5CH Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field name IStsResVal IStsCfgCop IStsDiff R W RW RW RW Reset value 0H 0H 0H Interrupt status register Bit 2 IStsResVal Interrupt status flags a 1 signifies that the corresponding interrupt condition occurred even if inte...

Page 628: ... 11 0 Sig_error_count The amount video frames with Signature errors Every Trigger see TriggerW0 will reset Signature_error to 0 SignatureARW0 Register address BaseAddress 68H Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field name SignatureARW0 R W R Reset value 0H Signature A Result channel R Bit 31 0 SignatureARW0 Signature A Result channel R S...

Page 629: ...0 9 8 7 6 5 4 3 2 1 0 Field name SignatureBGW0 R W R Reset value 0H Signature B Result channel G Bit 31 0 SignatureBGW0 Signature B Result channel G SignatureBBW0 Register address BaseAddress 7CH Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field name SignatureBBW0 R W R Reset value 0H Signature B Result channel B Bit 31 0 SignatureBBW0 Signature...

Page 630: ...rocessing Flow Figure 21 2 SIG Processing Flow 21 5 2 Processing Algorithm Please see chapter 21 3 Checksum generations are possible for each incoming pixel frame When a generation is triggerered after each incoming pixel frame a set of signature checksum results is valid ...

Page 631: ...l V1 64 21 13 21 6Control Flow 21 6 1 Example Control Flow IStsCfgCopy Config Bus wr 0 rd 0 CtrlCfg trigger Status pending Status active Frame Start IStsResValid wr 1 wr 2 rd 1 rd 2 Cleared by SW Figure 21 3 Example Control Flow 1 ...

Page 632: ...e A B blue window Write window yellow coordinates Write reference values for Signature A for yellow window Write reference values for Signature B Set threshold for B for yellow window Setup single TriggerMode Trigger generation by writing 1 to the trigger field Interrupt CfgCop ResVal Waiting for Interrupt VerticalUpperLeft green VerticalLowerRight green VerticalUpperLeft yellow VerticalLowerRight...

Page 633: ...ase for calculation n Write Window n coordinates Setup single TriggerMode Trigger one generation by writing to the trigger field On IStsResVal Read result registers Signature A B Process results 21 6 3 Cyclic Signature Generation with every incoming frame CYCLIC monitoring of one window General Configuration phase most registers are not shadowed Enable mask mode Write mask window coordinates Enabl...

Page 634: ...ld Wait on interrupt or poll IStsDiff On IStsDiff Read result registers Signature A B Process results Before display content of evaluation window changes Cancel cyclic trigger and reprogram reference values 21 6 5 Limitation of Cyclic Signature Generation It is not recommended to change evaluation window coordinates and relating reference values during cyclic continuous monitoring mode Reference v...

Page 635: ...ls conforming to the RSDS standard Reduced Swing Differential Signal The module consists of three submodules a Timing Signal Generator TSIG module an RSDS bit mapping module RBM and an IO module for control of special RSDS or TTL capable IO cells The TSIG IP is derived from Fujitsu s MB87P2020 Jasmine SyncSig IP please refer to the MB87P2020 Hardware Manual 22 3 Feature List RBM RSDS Bit Mapping C...

Page 636: ... Inversion control signal for transition minimizing useful for TTL applications Compared to MB87P2020 Jasmine s SyncSig IP this IP provides 12 instead of 6 pulse generators 12 instead of 8 sync mixers Inversion control signal Toggling feature for pulse generators Active high reset value for 2 signals IO module Control of combined TTL RSDS IO cells Output RSDS clock Output TTL clock 90 phase shift ...

Page 637: ...1 clears the register Reset value Reset value indicates the value of each bit field immediately after reset 0 Initial value is 0 1 Initial value is 1 X Undefined Unused register fields are marked with a solid grey background Bit vectors are unsigned integers if nothing else specified Please note that access to an address with no register results in an error response Global Address For module base ...

Page 638: ...ase address 440H DIR_SPG3MaskOff Base address 444H DIR_SPG4PosOn Sync pulse generator 4 Switch on position Base address 448H DIR_SPG4MaskOn Base address 44CH DIR_SPG4PosOff Sync pulse generator 4 Switch off position Base address 450H DIR_SPG4MaskOff Base address 454H DIR_SPG5PosOn Sync pulse generator 5 Switch on position Base address 458H DIR_SPG5MaskOn Base address 45CH DIR_SPG5PosOff Sync pulse...

Page 639: ...address 4C0H DIR_SPG11MaskOff Base address 4C4H DIR_SSqCycle Base address 4C8H DIR_SMx0Sigs Sync mixer 0 signal selection Base address 4CCH DIR_SMx0FctTable Sync mixer output function table a a s4 24 s3 23 s2 22 s1 21 s0 20 Base address 4D0H DIR_SMx1Sigs Sync mixer 1 signal selection Base address 4D4H DIR_SMx1FctTable Sync mixer output function table a a s4 24 s3 23 s2 22 s1 21 s0 20 Base address ...

Page 640: ... 520H DIR_SMx11Sigs Sync mixer 11 signal selection Base address 524H DIR_SMx11FctTable Sync mixer output function table a a s4 24 s3 23 s2 22 s1 21 s0 20 Base address 528H DIR_SSwitch Sync switch Base address 52CH DIR_RBM_CTRL RSDS Bitmap Control Base address 534H DIR_PIN0_CTRL IO Module Pad 0 Control Base address 538H DIR_PIN1_CTRL IO Module Pad 1 Control Base address 53CH DIR_PIN2_CTRL IO Module...

Page 641: ...R_SPG0PosOn Register address BaseAddress 404H Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field name SPGPSON_TOGGLE0 SPGPSON_X0 Reserved SPGPSON_Y0 R W RW RW RW RW Reset value 0H 0H 0H 0H Sync pulse generator 0 Switch on position Bit 31 SPGPSON_TOGGLE0 Toggle enable 0b disable 1b enable Bit 30 16 SPGPSON_X0 X scan position Bit 15 Reserved Do not...

Page 642: ..._SPG1MaskOn Register address BaseAddress 418H Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field name SPGMKON1 R W RW Reset value 0H Bit 30 0 SPGMKON1 mask bits 1 do not include this bit into position matching DIR_SPG1PosOff Register address BaseAddress 41CH Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 ...

Page 643: ... 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field name SPGPSOFF_TOGGLE2 SPGPSOFF_X2 Reserved SPGPSOFF_Y2 R W RW RW RW RW Reset value 0H 0H 0H 0H Sync pulse generator 2 Switch off position Bit 31 SPGPSOFF_TOGGLE2 Toggle enable 0b disable 1b enable Bit 30 16 SPGPSOFF_X2 X scan position Bit 15 Reserved Do not modify Bit 14 0 SPGPSOFF_Y2 Y scan position DIR_SPG2MaskOff Register address BaseAddress 430H Bit numbe...

Page 644: ...9 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field name SPGMKOFF3 R W RW Reset value 0H Bit 30 0 SPGMKOFF3 Mask bits 0b include bit in position matching 1b do not include this bit in position matching DIR_SPG4PosOn Register address BaseAddress 444H Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field name SPGPSON_TOGGLE4 SPGPSON_X4 Reserved SPG...

Page 645: ...X5 Reserved SPGPSON_Y5 R W RW RW RW RW Reset value 0H 0H 0H 0H Sync pulse generator 5 Switch on position Bit 31 SPGPSON_TOGGLE5 Toggle enable 0b disable 1b enable Bit 30 16 SPGPSON_X5 X scan position Bit 15 Reserved Do not modify Bit 14 0 SPGPSON_Y5 Y scan position DIR_SPG5MaskOn Register address BaseAddress 458H Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 ...

Page 646: ...ld name SPGMKON6 R W RW Reset value 0H Bit 30 0 SPGMKON6 Mask bits 0b include bit in position matching 1b do not include this bit in position matching DIR_SPG6PosOff Register address BaseAddress 46CH Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field name SPGPSOFF_TOGGLE6 SPGPSOFF_X6 Reserved SPGPSOFF_Y6 R W RW RW RW RW Reset value 0H 0H 0H 0H Sy...

Page 647: ...n Bit 31 SPGPSOFF_TOGGLE7 Toggle enable 0b disable 1b enable Bit 30 16 SPGPSOFF_X7 X scan position Bit 15 Reserved Do not modify Bit 14 0 SPGPSOFF_Y7 Y scan position DIR_SPG7MaskOff Register address BaseAddress 480H Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field name SPGMKOFF7 R W RW Reset value 0H Bit 30 0 SPGMKOFF7 Mask bits 0b include bit ...

Page 648: ... include bit in position matching 1b do not include this bit in position matching DIR_SPG9PosOn Register address BaseAddress 494H Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field name SPGPSON_TOGGLE9 SPGPSON_X9 Reserved SPGPSON_Y9 R W RW RW RW RW Reset value 0H 0H 0H 0H Sync pulse generator 9 Switch on position Bit 31 SPGPSON_TOGGLE9 Toggle ena...

Page 649: ... enable 0b disable 1b enable Bit 30 16 SPGPSON_X10 X scan position Bit 15 Reserved Do not modify Bit 14 0 SPGPSON_Y10 Y scan position DIR_SPG10MaskOn Register address BaseAddress 4A8H Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field name SPGMKON10 R W RW Reset value 0H Bit 30 0 SPGMKON10 Mask bits 0b include bit in position matching 1b do not i...

Page 650: ...ching 1b do not include this bit in position matching DIR_SPG11PosOff Register address BaseAddress 4BCH Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field name SPGPSOFF_TOGGLE11 SPGPSOFF_X11 Reserved SPGPSOFF_Y11 R W RW RW RW RW Reset value 0H 0H 0H 0H Sync pulse generator 11 Switch off position Bit 31 SPGPSOFF_TOGGLE11 toggle enable 0b disable 1...

Page 651: ...table DIR_SMx1Sigs Register address BaseAddress 4D0H Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field name SMX1SIGS_S4 SMX1SIGS_S3 SMX1SIGS_S2 SMX1SIGS_S1 SMX1SIGS_S0 R W RW RW RW RW RW Reset value 0H 0H 0H 0H 0H Sync mixer 1 signal selection Bit 14 12 SMX1SIGS_S4 select 4 000b const zero 001b sync sequencer output 010b 111b sync pulse generato...

Page 652: ...eset value 0H 0H 0H 0H 0H Sync mixer 3 signal selection Bit 14 12 SMX3SIGS_S4 select 4 000b const zero 001b sync sequencer output 010b 111b sync pulse generator output Bit 11 9 SMX3SIGS_S3 select 3 Bit 8 6 SMX3SIGS_S2 select 2 Bit 5 3 SMX3SIGS_S1 select 1 Bit 2 0 SMX3SIGS_S0 select 0 DIR_SMx3FctTable Register address BaseAddress 4E4H Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14...

Page 653: ...Bit 5 3 SMX5SIGS_S1 select 1 Bit 2 0 SMX5SIGS_S0 select 0 DIR_SMx5FctTable Register address BaseAddress 4F4H Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field name SMXFCT5 R W RW Reset value 0H Sync mixer output function table a a s4 24 s3 23 s2 22 s1 21 s0 20 Bit 31 0 SMXFCT5 Sync mixer 0 function table DIR_SMx6Sigs Register address BaseAddress...

Page 654: ... 12 11 10 9 8 7 6 5 4 3 2 1 0 Field name SMXFCT7 R W RW Reset value 0H Sync mixer output function table a a s4 24 s3 23 s2 22 s1 21 s0 20 Bit 31 0 SMXFCT7 Sync mixer 0 function table DIR_SMx8Sigs Register address BaseAddress 508H Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field name SMX8SIGS_S4 SMX8SIGS_S3 SMX8SIGS_S2 SMX8SIGS_S1 SMX8SIGS_S0 R ...

Page 655: ...R_SMx10Sigs Register address BaseAddress 518H Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field name SMX10SIGS_S4 SMX10SIGS_S3 SMX10SIGS_S2 SMX10SIGS_S1 SMX10SIGS_S0 R W RW RW RW RW RW Reset value 0H 0H 0H 0H 0H Sync mixer 10 signal selection Bit 14 12 SMX10SIGS_S4 select 4 000b const zero 001b sync sequencer output 010b 111b sync pulse generato...

Page 656: ...e delay of pixel clock DIR_RBM_CTRL Register address BaseAddress 52CH Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field name ColOrder BitOrder swapoddevenbit BitPerCol IfcType Bypass R W RW RW RW RW RW RW Reset value 0H 0H 0H 0H 0H 1H RSDS Bitmap Control Bit 10 8 ColOrder Color Component Ordering 000b RGB 001b BRG 010b GBR 011b RBG 100b GRB 101b...

Page 657: ...on for Pad i 1 for RSDS 00b channel i 01b channel i 1 10b clk 11b const0 for TTL 00b channel i 2 01b channel i 2 1 10b clk 11b const0 Bit 14 NDelay1 N pin Padcell 1 delay 0b no delay 1b half bitclock cycle delay TTL mode only Bit 13 Delay1 Pad 1 delay 0b no delay 1b half bit clock cycle delay Bit 7 InOut1 output enable control 0b input enabled 1b output enabled Bit 6 NPolarity1 N pin of Padcell 1 ...

Page 658: ... 3 drive mode 0b differential 1b TTL Bit 1 0 Boost3 Boost factor for drive current x0b 2mA x1b 4mA only boost 0 has effect DIR_PIN4_CTRL Register address BaseAddress 544H Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field name NChanSel4ChanSel4 NDelay4Delay4 InOut4 NPolarity4 Polarity4 Mode4 Boost4 R W RW RW RW RW RW RW RW RW RW Reset value 0H 0H...

Page 659: ...lection for N Pin of Pad i 6 TTL 00b channel i 2 1 01b channel i 2 10b clk 11b const0 TTL mode only Bit 18 17 ChanSel6 Channel selection for Pad i 6 for RSDS 00b channel i 01b channel i 1 10b clk 11b const0 for TTL 00b channel i 2 01b channel i 2 1 10b clk 11b const0 Bit 14 NDelay6 N pin Padcell 6 delay 0b no delay 1b half bit clock cycle delay TTL mode only Bit 13 Delay6 Pad 6 delay 0b no delay 1...

Page 660: ...dcell 8 drive polarity TTL 0 normal 1 inverted RSDS no effect Bit 5 Polarity8 Pad 8 drive polarity TTL 0 normal 1 inverted RSDS 1 normal 0 inverted Bit 4 Mode8 Pad 8 drive mode 0b differential 1b TTL Bit 1 0 Boost8 Boost factor for drive current x0b 2mA x1b 4mA only boost 0 has effect DIR_PIN9_CTRL Register address BaseAddress 558H Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 1...

Page 661: ...0 9 8 7 6 5 4 3 2 1 0 Field name NChanSel11ChanSel11 NDelay11Delay11 InOut11 NPolarity11 Polarity11 Mode11 Boost11 R W RW RW RW RW RW RW RW RW RW Reset value 0H 0H 0H 0H 0H 0H 0H 1H 0H IO Module Pad 11 Control Bit 20 19 NChanSel11 Channel selection for N Pin of Pad i 11 TTL 00b channel i 2 1 01b channel i 2 10b clk 11b const0 TTL mode only Bit 18 17 ChanSel11 Channel selection for Pad i 11 for RSD...

Page 662: ...lf bit clock cycle delay TTL mode only Bit 13 Delay12 Pad 12 delay 0b no delay 1b half bit clock cycle delay Bit 7 InOut12 output enable control 0b input enabled 1b output enabled Bit 6 NPolarity12 N pin of Padcell 12 drive polarity TTL 0 normal 1 inverted RSDS no effect Bit 5 Polarity12 Pad 12 drive polarity TTL 0 normal 1 inverted RSDS 1 normal 0 inverted Bit 4 Mode12 Pad 12 drive mode 0b differ...

Page 663: ...on Modes The TCON module is either active or in bypass mode Register RBM_DIR_CTRL bypass In bypass mode the RGB data from the RGB source is transmitted unchanged through the RBM submodule Additional 3 timing signals HSYNC VSYNC DE from the frame generator are bypassed to the TSIG output signals TSIG 0 2 The RGB data and the 3 timing signals have the same latency ...

Page 664: ...guring TCON it is therefore necessary to setup the video frame HTP VTP HDP VDP in module DISP to provide a valid video frame to TCON module Otherwise no RGB and display clock data is output Configuration registers are not reseted by SW reset only internal states of TCON 22 5 2 3 RSDS Bitmap Mdule RBM 22 5 2 3 1 Block Diagram The following block diagram shows the functional design of the RBM module...

Page 665: ...ing RSDS 6bpc TTL 8bpc Rising Falling Ch0 R0 R0 Ch1 R1 R1 Ch2 R2 R2 Ch3 R3 R3 Ch4 R4 R4 Ch5 R5 R5 Ch6 R6 R6 Ch7 R7 R7 Ch8 G0 G0 Ch9 G1 G1 Ch10 G2 G2 Ch11 G3 G3 Ch12 G4 G4 Ch13 G5 G5 Ch14 G6 G6 Ch15 G7 G7 Ch16 B0 B0 Ch17 B1 B1 Ch18 B2 B2 Ch19 B3 B3 Ch20 B4 B4 Ch21 B5 B5 Ch22 B6 B6 Ch23 B7 B7 Table 22 3 Bitmapping TTL 8bpc TTL 6bpc Rising Falling Ch0 R2 R2 Ch1 R3 R3 Ch2 R4 R4 Ch3 R5 R5 Ch4 R6 R6 Ch5...

Page 666: ...h13 B3 B3 Ch14 B4 B4 Ch15 B5 B5 Ch16 B6 B6 Ch17 B7 B7 Ch18 0 0 Ch19 0 0 Ch20 0 0 Ch21 0 0 Ch22 0 0 Ch23 0 0 Table 22 4 Bitmapping TTL 6bpc 22 5 2 4 Timing Signal Module TSIG 22 5 2 4 1 Block Diagram The following block diagram shows the functional design of the TSIG module note the stages ...

Page 667: ... generated using a three stage approach in order to achieve maximum flexibility In the first stage signals are generated which carry positional timing information Two methods are used to create these signals The second stage combines them to form more complex waveforms The third stage is used to create a programmable delay of half a pixel clock cycle 22 5 2 4 3 Position Matching One way to form th...

Page 668: ...tched at the same time the output of the sync pulse generator is reset TOGGLE_MODE ON The output of a sync pulse generator toggles if the current position equals the respective programmable position in all bits for which its don t care vector which is also programmable contains zeros Toggle mode allows e g frame wise toggling signals Set Reset overrides toggle and if both positions match and toggl...

Page 669: ... match This match address increment cycle continues until the programmed sequence length is reached If the last position is matched the address counter is reset to zero again and the cycle starts again It is thus possible to generate arbitrarily complex waveforms with up to 64 edges which is the maximum sequence length 22 5 2 4 5 Combining First Stage Sync Signals As shown above there are twelve s...

Page 670: ...lected These are referred to then as S0 S4 and form the address for the function table This function table is used to look up the result of the Boolean operation the five selected signals shall be subject to An example may help understand the topic Assuming the outputs of three Sync Pulse Generators shall form a combined signal with the function one would proceed as follows At first the Sync Mixer...

Page 671: ...nc Mixers are connected to actual GDC pins they are fed through a programmable delay stage This allows the signals either to be left untouched or delayed for half a pixel clock cycle This delay can be set for each of the twelve Sync Mixer output signals individually with the Sync Switch register 22 5 2 5 Inversion Signal Generation The purpose of the inversion signal INV is the minimization of tot...

Page 672: ...MB86R02 Jade D Hardware Manual V1 64 22 38 22 5 2 6 Bypass Mode 22 5 2 6 1 Pin mapping Bypass Mode Data Figure 22 8 Pin Mapping Bypass Mode data ...

Page 673: ..._RSCK Frequency MHz 42 0 t_RSCK period ns 23 810 RSCKH High Period ns 10 405 C_L 5pF RSCKL Low Period ns 10 405 C_L 5pF Duty cycle 48 50 52 RSTr f Rise Fall Time ns 1 5 TSIGSU setup time ns 9 0 C_L 15pF SSWITCH i 0 TSIGHD hold time ns 9 0 C_L 15pF SSWITCH i 0 TTL operation mode DISPSU setup time ns 4 0 C_L 5pF Delay i 0 DISPHD hold time ns 4 0 C_L 5pF Delay i 0 f_TTLCK Frequency MHz 42 0 t_TTLCK p...

Page 674: ...Register DIR_Pin_ctrl j Delay 0 RSCKH RSCKL 50 RSDAT pins DISP i Registers DIR_Pin_ctrl i Delay 1 RSHD RSSU RSHD RSSU 0V diff Pins TSIG i Register Dir_SSwitch SSwitch 0 TSIGHD TSIGSU TTL diff Figure 22 9 RSDS operation Output Timing Figure 22 10 Rise Fall Times ...

Page 675: ...ir_SSwitch SSwitch 0 TSIGHD TSIGSU TTLCK pin DISP j Register DIR_Pin_ctrl j Delay 0 Register DIR_Pin_Ctrl j Polarity 1 Figure 22 12 TTL operation output timing 2 22 5 3 Limitations Several configuration registers only have an effect with TTL mode enabled These registers are marked TTL mode only Reprogramming of configuration registers during active display can cause undefined effects Only word acc...

Page 676: ...4 15 14 15 14 15 14 15 14 15 14 15 14 15 14 15 clk 18 19 18 19 18 19 10 d 18 19 18 19 18 19 18 19 18 19 18 19 18 19 18 19 18 19 18 19 clk 20 21 20 21 11 d 20 21 20 21 20 21 20 21 20 21 20 21 20 21 20 21 20 21 20 21 20 21 clk 22 23 12 d 22 23 22 23 22 23 22 23 22 23 22 23 22 23 22 23 22 23 22 23 22 23 22 23 clk 22 6 1 3 Pin mapping TTL In single ended TTL mode each of the 24 output pins can be used...

Page 677: ...MB86R02 Jade D Hardware Manual V1 00 FUJITSU PROPRIETARY AND CONFIDENTIAL DRAFT 22 2 Chip Board clock clock double drive clock Figure 22 13 Pin Mapping TTL ...

Page 678: ......

Page 679: ... 12 12 12 12 12 clk 13 13 13 13 13 13 13 13 13 13 13 7 a0 13 13 13 13 13 13 13 13 13 13 13 13 13 13 clk 14 14 14 14 14 14 14 14 14 14 a1 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 clk 15 15 15 15 15 15 15 15 15 8 a0 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 clk 16 16 16 16 16 16 16 16 a1 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 clk 17 17 17 17 17 17 17 9 a0 17 17 17 17 17 17 17 1...

Page 680: ......

Page 681: ... 8 8 8 8 7 a1 8 8 8 8 8 8 8 8 8 clk 9 9 9 9 9 9 9 9 9 9 8 5 a0 9 9 9 9 9 9 9 9 9 9 clk 10 10 10 10 10 10 10 10 10 9 a1 10 10 10 10 10 10 10 10 10 10 10 clk 11 11 11 11 11 11 11 11 10 6 a0 11 11 11 11 11 11 11 11 11 11 11 11 clk 12 12 12 12 12 12 12 11 a1 12 12 12 12 12 12 12 12 12 12 12 12 12 clk 13 13 13 13 13 13 12 7 a0 13 13 13 13 13 13 13 13 13 13 13 13 13 13 clk 14 14 14 14 14 13 a1 14 14 14 ...

Page 682: ...22 2 MB86R02 Jade D Hardware Manual V1 00 FUJITSU PROPRIETARY AND CONFIDENTIAL ...

Page 683: ...steps for a panel driver routine in principle Of course a lot of panel timing relevant parameters are configured at the DISP module This is not covered in this section Some decisions must already be taken when designing the board selecting the used panel driver ICs etc The diagram does not show the detailed flow and exact order of configuration steps for one application ...

Page 684: ...22 2 MB86R02 Jade D Hardware Manual V1 00 FUJITSU PROPRIETARY AND CONFIDENTIAL Figure 22 14 TCON flow diagram ...

Page 685: ...the LSI AHB M HDMAC 8ch S S SRAM 32KB RLD S CCPB MEMC SRAM 32KB S S MLB AHB2AXI M S S Data input flow Data output flow M Figure 23 2 Example position in LSI Phase 1 HDMAC initiates a transfer form CCBP to RLD Data will be latched into HDMAC s FIFO Phase2 HDMAC prompts FIFO data to input FIFO of RLD Phase3 RLD decompresses the FIFO data and transfers them to Target destination ...

Page 686: ...y be an arbitrary AHB slave of the system 23 3 Feature List Support of a simple run length compressing format TGA like format see also Fujitsu s MB87P2020A Jasmine Hardware Manual 1 2 4 8 16 24 32 bit per pixel formats supported AHB master for data output FIFO for data input and output allows burst access of AHB 23 3 1 References Truevision TGA FILE FORMAT SPECIFICATION Truevision Inc Version 2 0 ...

Page 687: ...NNN NNN_NNNN 1 x4 bits with color data CCCC CCCC bit aligned 8bpp Compressed 1NNN NNNN 1 color byte CCCC CCCC uncompressed 0NNN NNNN NNN_NNNN 1 bytes with color data CCCC CCCC 16bpp 1 Compressed 1NNN NNNN 2 bytes color data CCCC CCCC CCCC CCCC uncompressed 0NNN NNNN NNN_NNNN 1 2 bytes with color data CCCC CCCC CCCC CCCC 24bpp Compressed 1NNN NNNN 3 bytes color data CCCC CCCC CCCC CCCC CCCC CCCC un...

Page 688: ...rd alignment memory stride calculation is supported in hardware The output data is organized as Big Endian 23 6Software Interface 23 6 1 Format of Register Description The register descriptions in the following sections use the format shown below to describe each bit field of a register Register address Offset Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4...

Page 689: ...s Register Name Description Base address 0H SWReset SW reset Base address 4H RldCfg general configuration register Base address 8H StrideCfg0 Stride general configuration register Base address CH StrideCfg1 Line Stride Length Base address 10H BYTECNT Target number of decompressed bytes Base address 14H OFIFO Output FIFO Control Base address 18H DestAddress Local AHB master transfer Destination add...

Page 690: ...Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field name StrideEn R W RW Reset value 0H Stride general configuration register Bit 0 StrideEn Enable for output data stride alligned 0b disabled no observation of LineLength and Stride needed for 4x4 1bpp sprites 1b enabled StrideCfg1 Register address BaseAddress CH Bit number 31 30 29 28 27 26 25 24 ...

Page 691: ... 8 7 6 5 4 3 2 1 0 Field name Reserved0 AHBMTransferWidth AHBMFixedDest R W RWS RW RW Reset value 0H 0H 0H Local AHB master transfer Configuration Control Bit 23 16 Reserved0 Bit 9 8 AHBMTransferWidth 00b byte 01b halfword 10b word 11b reserved Bit 0 AHBMFixedDest 0b destination address is incremented 1b destination address is fixed RLDCtrl Register address BaseAddress 20H Bit number 31 30 29 28 2...

Page 692: ...egister Bit 4 Reserved Bit 3 IFIFOempty Input FIFO currently empty Bit 2 OFIFOfull Output FIFO currently full Bit 1 IFIFOfull Input FIFO currently full Bit 0 Busy RLD busy SAHBData Register address BaseAddress 30H Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field name InData R W RW Reset value 0H AHB Slave Input Data Bit 31 0 InData RLD input da...

Page 693: ...modes in operation mode and disabled mode 23 8Control Flow 23 8 1 Example Control Flow 1 microcontroller decodes TGA header info o BitPerPixel o Source size o picture dimensions number of decompressed bytes configuration of RLD 2 reset OFIFO IFIFO 3 set bpp format 4 set target number of bytes 5 Configure AHB master IF o e g Dest Address in Video Memory 6 Enable RLD Deliver compressed data to RLD A...

Page 694: ...sed data source is AHB master 1 Write actively data to RLD AHB slave 2 interrupt after completion 23 9 Limitations 23 9 1 AHBMTransferWidth Setup It is recommended to set the register AHBMTransferWidth depends on the LSBs of BYTCNT according following table BYTECNT LSB 1 0 AHBMCtrl AHBMTransferWidth 00 Word b10 Halfword b01 Byte b00 01 Byte b00 10 Halfword b01 Byte b00 11 Byte b00 ...

Page 695: ...s Please refer to 1 6 1 Pin Multiplex for shared peripherals The data read write and direction are controlled via the GPIO control register 24 2Feature The GPIO module has the following features 24 bit GPIO port Composed of the following 2 registers Port data register GPDR Data direction register GPDDR 24 3Block diagram Figure 24 2 Block diagram of a GPIO module shows the block diagram of the GPIO...

Page 696: ...DISP1N DISP11P DISP11N 24 4Supply clock The APB clock is supplied to the GPIO module Please refer to 5 Clock reset generator CRG for the frequency setting and control specifications of the APB clock 24 5Limitations If GPIO functionality is mapped to pins DISPxP N see MPXTABLE3 chapter 1 6 1 Pin Multiplex then direction control can only be applied pairwise for P and N pins together That means only ...

Page 697: ...O_PD 7 0 pin 04H Port data register 1 GPDR1 Setting of input output data of GPIO_PD 15 8 pin 08H Port data register 2 GPDR2 Setting of input output data of GPIO_PD 23 16 pin 0CH Reserved Reserved area access prohibited 10H Data direction register 0 GPDDR0 Control of input output direction of GPIO_PD 7 0 pin 14H Data direction register 1 GPDDR1 Control of input output direction of GPIO_PD 15 8 pin ...

Page 698: ... 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name R W Initial value Meaning of item and sign Address Address base address offset address of the register Bit Bit number of the register Name Bit field name of the register R W Attribution of read write of each bit field R0 Read value is always 0 R1 Read value is always 1 W0 Write value is always 0 and write access of 1 is ignored W1 Write value is always 1 and w...

Page 699: ...ved PDR0_7 PDR1_1 5 PDR2_2 3 PDR0_6 PDR1_1 4 PDR2_2 2 PDR0_5 PDR1_1 3 PDR2_2 1 PDR0_4 PDR1_1 2 PDR2_2 0 PDR0_3 PDR1_1 1 PDR2_1 9 PDR0_2 PDR1_1 0 PDR2_1 8 PDR0_1 PDR1_9 PDR2_1 7 PDR0_0 PDR1_8 PDR2_1 6 R W R W R W R W R W R W R W R W R W Initial value X X X X X X X X X X X X X X X X Bit field Description No Name 31 8 Reserved Reserved bits Write access is ignored Read value of these bits is undefine...

Page 700: ...ions of GPIO_PD 15 GPIO_PD 8 pins are determined by the corresponding bit of GPDDR1 register Initial value of these bits is undefined 7 0 PDR2_23 16 GPDR2 register s bit field This register is setting register of GPIO_PD 23 16 pin s input output data and each bit corresponds to GPIO pin as follows PDR2_23 GPIO_PD 23 pin PDR2_22 GPIO_PD 22 pin PDR2_21 GPIO_PD 21 pin PDR2_20 GPIO_PD 20 pin PDR2_19 G...

Page 701: ...6 DDR1_1 4 DDR2_2 2 DDR0_5 DDR1_1 3 DDR2_2 1 DDR0_4 DDR1_1 2 DDR2_2 0 DDR0_3 DDR1_1 1 DDR2_1 9 DDR0_2 DDR1_1 0 DDR2_1 8 DDR0_1 DDR1_9 DDR2_1 7 DDR0_0 DDR1_8 DDR2_1 6 R W R W R W R W R W R W R W R W R W Initial value X X X X X X X X 0 0 0 0 0 0 0 0 Bit field Description No Name 31 8 Reserved Reserved bits Write access is ignored Read value of these bits is undefined 7 0 DDR0_7 0 GPDR0 register s bi...

Page 702: ...IO_PD 12 pin DDR1_11 GPIO_PD 11 pin DDR1_10 GPIO_PD 10 pin DDR1_9 GPIO_PD 9 pin DDR1_8 GPIO_PD 8 pin These bits are initialized to 1 by reset GPDDR2 register s bit field This register controls input output directions of GPIO_PD 23 16 pin 0 GPIO acts as an input port 1 GPIO acts as an output port GPIO pin corresponding to this register is as follows DDR2_23 GPIO_PD 23 pin DDR2_22 GPIO_PD 22 pin DDR...

Page 703: ...PIO port s direction 24 7 2 Data transfer When a GPIO port is used as an input port DDRx 0 the data signal input to the port input signal PI is stored in PDRx in on the rising edge of the APB clock see Figure 13 1 Input data can be read via the GPDRx register During the period write access to the GPDRx register is valid and PDRx out is changeable except when DDRx 0 When the GPIO port is used as an...

Page 704: ...lse Width Modulator units 25 1 Outline MB86R02 has 8 PWM channels which are able to output high precision PWM wave patterns efficiently 25 2 Feature The PWM unit has the following features 8 embedded channels Individual settings possible for duty ratio phase and polarity Configurable one shot output continuous output of the pulse ...

Page 705: ...w CCNT JCNT registers Set to CMPX_MODE_6 1B of multiplex mode setting register to make PWM 7 4 available Set to CMPX_MODE_7 0B of multiplex mode setting register to make PWM 3 0 available 25 5 Clock Supply The APB clock is supplied to the PWM unit Please refer to the chapter Clock Reset Generator CRG for details on setting the frequency and controlling the clock 25 6 Interrupts When an interrupt v...

Page 706: ...gister PWM0SR Setting start stop of PWM 18H PWM ch0 current count register PWM0CCR Indicating current count value in the BASECLK base 1CH PWM ch0 interrupt register PWM0IR Selecting cause of PWM interrupt factor PWM ch1 PWM ch3 PWM ch5 PWM ch7 FFF4_1100H FFF4_6100H FFF4_7100H FFF4_8100H 00H PWM ch1 base clock register PWM1BCR Setting base clock of PWM cycle Output pin PWM_O1 PWM_O3 PWM_O5 PWM_O7 0...

Page 707: ...3 12 11 10 9 8 7 6 5 4 3 2 1 0 Name R W Initial value Meaning of item and sign Address Address base address offset address of the register Bit Bit number of the register Name Bit field name of the register R W Attribution of read write of each bit field R0 Read value is always 0 R1 Read value is always 1 W0 Write value is always 0 and write access of 1 is ignored W1 Write value is always 1 and wri...

Page 708: ... 18 17 16 Name Reserved R W R R R R R R R R R R R R R R R R Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name BCR 15 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit field Description No Name 31 16 Reserved Reserved bits Write access is ignored The read value of these bits is always 0 ...

Page 709: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name TPR 15 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit field Description No Name 31 16 Reserved Reserved bits Write access is ignored The read value of these bits is always 0 15 0 TPR Cycle length of 1 pulse shown in Figure 14 2 is set TPR 15 0 Pulse cy...

Page 710: ... R R Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name PR 15 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit field Description No Name 31 16 Reserved Reserved bits Write access is ignored The read value of these bits is always 0 15 0 PR Phase cycle shown in Figure 14 3 is set PR 15 0 ...

Page 711: ... R R Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name DR 15 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit field Description No Name 31 1 6 Reserved Reserved bits Write access is ignored The read value of these bits is always 0 15 0 DR Duty cycle shown in Figure 14 4 is set DR 15 0 ...

Page 712: ...0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Reserved ONESHOT Reserved POL R W R R R R R R R R R R R R R W R W R W R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit field Description No Name 31 4 Reserved Reserved bits Write access is ignored The read value of these bits is always 0 3 ONESHOT Pulse output format either continuous output or one shot output is set 0 Continuous output ini...

Page 713: ...16 Name Reserved R W R R R R R R R R R R R R R R R R Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Reserved START R W R R R R R R R R R R R R R R R R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit field Description No Name 31 1 Reserved Reserved bits Write access is ignored The read value of these bits is always 0 0 START Start up Stop of PWM are...

Page 714: ...28 27 26 25 24 23 22 21 20 19 18 17 16 Name Reserved R W R R R R R R R R R R R R R R R R Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name CCR 15 0 R W R R R R R R R R R R R R R R R R Initial value X X X X X X X X X X X X X X X X Bit field Description No Name 31 16 Reserved Reserved bits Write access is ignored The read value of these bits is always 0 15 ...

Page 715: ...E R W R R R R R R R W R W R R R R R R R W1 R W1 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit field Description No Name 31 10 Reserved Reserved bits Write access is ignored The read value of these bits is always 0 9 8 INTREP 1 0 The bit DONE bit which might be the cause of PWM interrupt is selected INTREP 1 0 Possible cause bit for PWM interrupt 00 DONE bit is not selected 01 DONE bit is selec...

Page 716: ...tus register PWMxCR Set PWMx activation register PWMxSR PWM is activated PWMx interrupt register s INTREP bit 01B Output 1 pulse cycle Yes Interrupt occurs No PWMxSR start bit 1 Yes No End PWM stops with negating start bit PWMxSR START bit at completing pulse cycle not immediately after negating the start bit Set each register in the following condition PWMx base clock register 1 PWMx phase regist...

Page 717: ...ration of A D value by analog data auto polling operation A D converter operation clock dividing ratio can be selected 1 4 APB clock is 41 5MHz Approx 648 4K samples sec 1 8 APB clock is 41 5MHz Approx 324 1K samples sec 1 16 APB clock is 41 5MHz Approx 162 0K samples sec 1 32 APB clock is 41 5MHz Approx 81 0K samples sec 1 64 APB clock is 41 5MHz Approx 40 5K samples sec 1 256 APB clock is 41 5MH...

Page 718: ... AD_VIN0 IN 1 A D analog input pin AD_VIN1 IN 1 A D analog input pin AD_VIN2 IN 1 A D analog input pin AD_VIN3 IN 1 A D analog input pin AD_VRH0 IN 1 Reference voltage H input pin AD_VRH1 IN 1 Reference voltage H input pin AD_VRL0 IN 1 Reference voltage L input pin AD_VRL1 IN 1 Reference voltage L input pin AD_VR0 OUT 1 Reference output AD_VR1 OUT 1 Reference output AD_AVD0 IN 1 Analog power suppl...

Page 719: ...0 1 2 AD_VIN2 1 0 1 AD_VIN1 1 3 AD_VIN3 26 7 Output truth value list Example of truth value of A D converter is shown below Ideal input level Output code VIN V D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 2 2485 H H H H H H H H H H 2 2471 2 2485 H H H H H H H H H L 2 2456 2 2471 H H H H H H H H L H 0 7515 0 7529 L L L L L L L L L H 0 7515 L L L L L L L L L L Note AD_AVD0 3 0V AD_VRH0 AD_VRH1 2 25V AD_ VRL0 AD_VR...

Page 720: ...re shows an analog pin s equivalent circuit of the A D converter Sample C Equivalent circuit in sampling period sample is internal signal VR0 Internal PD 2 RR 2 RR Internal PD 2 RR AVD0 AD_AVS1 2 RR Internal PD AD_VRH0 AD_VRH1 AD_VRL0 AD_VRL1 VIN0 VIN1 Figure 26 2 Analog pin s equivalent circuit ...

Page 721: ...er down mode is set released 0CH Reserved Reserved area access prohibited 10H ADC 0 clock selection register ADC0CKSEL Clock frequency is supplied to A D converter 14H ADC 0 status register ADC0STATUS A D converted data is stored to data register ADC 1 FFF5_3000H 00H ADC 1 data register ADC1DATA A D converted data is stored 04H ADC1 mode register ADC1MODE Sampling mode is set 08H Down of ADC 1 pow...

Page 722: ...the address Offset address of the register Bit number Bit number shows bit position of the register Field name Field name shows bit name of the register R W R W shows the read write attribute of each bit field R Read W Write W1C Writing a value of 1 clears the register Reset value Reset value indicates the value of each bit field immediately after reset 0 Initial value is 0 1 Initial value is 1 X ...

Page 723: ...always 0 9 0 DATA0 9 0 Output data from A D converter input 0 is stored with polling operation When power down mode is set to release at ADCx power down control register ADCxXPD data is imported to this register 26 9 4 ADCx mode register ADCxMODE This register is to set the sampling mode Address instance 0 FFF5_2000 04H instance 1 FFF5_3000 04H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 N...

Page 724: ...s written to XPD bit A D converter s power down mode is released and A D data polling starts Writing 0 to the bit sets A D converter s power down mode and A D data polling stops 26 9 6 ADCx clock selection register ADCxCKSEL This register is to se to specify ADC clock frequency supplying to A D converter This setting enables sampling plate change Address instance 0 FFF5_2000 10H instance 1 FFF5_30...

Page 725: ...nverter CKSEL 2 0 Clock frequency setting Sampling late samples sec 000B 1 4096 0 6K 001B 1 1024 2 5K 010B 1 256 10 1K 011B 1 64 40 5K 100B 1 32 81 0K 101B 1 16 162 0K 110B 1 8 324 1K 111B 1 4 648 4K This clock is made dividing APB clock 41 5MHz Analog voltage sampling is carried out every 16 cycles of clock set in this register ...

Page 726: ...erved bit Write access is ignored Read value of these bits is always 0 1 CMP1 Whether A D data conversion is completed for input 1 is indicated 0 A D data conversion is not completed initial value 1 A D data conversion is completed At the time data is set to ADCxDATA CMP bit becomes 1 Writing 0 to the bit clears register value although 1 is written to CMP bit register bit value does not change Set...

Page 727: ...ta value is updated only every 16 ADC clocks though ADCxDATA register can be read at any time In mode 2 b10 every data result is only sampled every 32 ADC clock cycles Set converted A D data to ADCxDATA register A range of data is 0x0 0x3FF The value of ADCxSTATUS register doesn t change if ADCxSTATUS register is 0x1 If ADCxSTATUS register is 0x0 the value of ADCxSTATUS register becomes 0x1 In ADC...

Page 728: ...l of each sub frame Setting valid invalid of each channel in each sub frame Note 1 Setting word length from 7 to 32 bit Programming frequency of frame synchronous signal Setting up to 3071 bit in 1 frame Programming width of frame synchronous signal 1 bit or 1 channel length Programming phase of frame synchronous signal 0 bits or 1 bit delay Setting polarity of frame synchronous signal Setting pol...

Page 729: ...Hardware Manual V1 64 27 3Block diagram Figure 27 1 shows block diagram of I2S As shown below MB86R02 has 1 I2S channel I2S0 Module I2S_SCK0 I2S_WS0 I2S_SDO0 AHB Bus MB86R02 HDMAC I2S_SDI0 Figure 27 1 Block diagram of I2S ...

Page 730: ...ty of I2S IF pins depends on follow registers of CCNT JCNT Set to CMPX_MODE_6 0B of multiplex mode setting register 27 5Supply clock AHB clock is supplied to I2S interface unit Refer to 5 Clock reset generator CRG for frequency setting and control specification of the clock ...

Page 731: ...gister FFEE_0008 I2S0CNTREG Control register FFEE_000C I2S0MCR0REG Channel control register 0 FFEE_0010 I2S0MCR1REG Channel control register 1 FFEE_0014 I2S0MCR2REG Channel control register 2 FFEE_0018 I2S0OPRREG Operation control register FFEE_001C I2S0SRST Software reset register FFEE_0020 I2S0INTCNT Interrupt control register FFEE_0024 I2S0STATUS STATUS register FFEE_0028 I2S0DMAACT DMA start u...

Page 732: ... 10 9 8 7 6 5 4 3 2 1 0 Name R W Initial value Meaning of item and sign Address Address base address offset address of the register Bit Bit number of the register Name Bit field name of the register R W Attribution of read write of each bit field R0 Read value is always 0 R1 Read value is always 1 W0 Write value is always 0 and write access of 1 is ignored W1 Write value is always 1 and write acce...

Page 733: ...egister is 1 it is written to reception FIFO after higher order bit is extended When frame is 2 sub frame construction and word length set to S0WDLN of MCR0REG register is 32 bit or less 16 bit when RHLL of CNTREG register is 1 reception data of sub frame 0 is written to reception FIFO after higher order bit is extended For the case that word length set to S1WDL of MCR0REG register is 32 bit or le...

Page 734: ...R W W W W W W W W W W W W W W W W W Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit field Description No Name 31 0 TXDATA 31 0 Word to be transmitted is able to be written as long as transmission FIFO is not full Write access is able to be performed regardless of shift register s operation status The word written to full transmission FIFO is actually not written Although writing data is accessed in wo...

Page 735: ...I2S_SCKx Setting examples are shown below External clock mode and external clock are 24 576MHz CKRT Dividing ratio I2S_SCKx 0x00 By pass 24 576MHz external clock is output as it is 0x01 1 2 12 288MHz 0x02 1 4 6 144MHz 0x03 1 6 4 096MHz 0x04 1 8 3 072MHz 0x05 1 10 2 458MHz Internal clock mode and AHB clock are 80MHz CKRT Dividing ratio I2S_SCKx 0x04 1 8 10MHz 0x05 1 10 8MHz 0x06 1 12 6 67MHz 0x07 1...

Page 736: ...idered to be used at protocol such as I2S and MSB Justified 0 32 bit FIFO word is handled as 1 word 1 32 bit FIFO word is handled as 2 words at serial bus with dividing 16 bit each to low order and high order They are transferred by serial bus in order of low order high order low order and high order At reception 2 consecutive words from serial bus is handled as low order and high order and they a...

Page 737: ...s specified 0 Data is driven at rising edge of I2S_SCKx and sampled at falling edge 1 Data is driven at falling edge of I2S_SCKx and sampled at rising edge 2 FSPH Phase is specified to I2S_WSx frame data 0 I2S_WSx becomes valid 1 clock before the first bit of frame data 1 I2S_WSx becomes valid at the same time as the first bit of frame data 1 FSLN Pulse width of I2S_WSx is specified 0 Pulse width ...

Page 738: ... 7 32 bit of channel length are available but 1 6 bit are prohibited S1CHN needs to be set to number of channel 1 Example 1 S1CHL 00110 Channel length becomes 7 bit Example 2 S1CHL 11111 Channel length becomes 32 bit Channel length is able to be set to 32 or less regardless of RHLL value of CNTREG register S1WDL is valid only in 2 sub frame construction SBFN of CNTREG is 1 and is invalid in 1 sub ...

Page 739: ...shorter than the one set to S0CHL 27 6 7 I2SxMCR1REG register This register controls enable and disable functions to each channel of sub frame 0 Address ch0 FFEE_0010 h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name S0C H31 S0C H30 S0C H29 S0C H28 S0C H27 S0C H26 S0C H25 S0C H24 S0C H23 S0C H22 S0C H21 S0C H20 S0C H19 S0C H18 S0C H17 S0C H16 R W R W R W R W R W R W R W R W R W R W R W R ...

Page 740: ...15 S1C H14 S1C H13 S1C H12 S1C H11 S1C H10 S1C H09 S1C H08 S1C H07 S1C H06 S1C H05 S1C H04 S1C H03 S1C H02 S1C H01 S1C H00 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit field Description No Name 31 0 S1CH31 S1CH00 Name S1CHxx of each bit indicates channel number xx of sub frame 1 e g S1CH00 bit controls 0th channel of sub frame 1 Th...

Page 741: ...eived from serial reception bus is not written to reception FIFO DMA reception channel stops during DMA transfer 1 Receiving operation is enabled 23 17 Reserved Reserved bits The write access is ignored The read value of these bits is always 0 16 TXENB Enable Disable functions of transmitting operation is set 0 Transmitting operation is disabled Reception FIFO becomes empty with writing 0 to this ...

Page 742: ...R R R R R R R R W Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit field Description No Name 31 1 Reserved Reserved bits The write access is ignored The read value of these bits is always 0 0 SRST Software reset is performed by writing 1 STATUS register and each internal state machine become initial state by software reset and transmission reception FIFO becomes empty There is no influence in registers...

Page 743: ...lock size error of transmission channel It becomes 1 by software reset 0 Interrupt to CPU by TBERR of STATUS register is not masked 1 Interrupt to CPU by TBERR of STATUS register is masked 28 FERRM This is frame error interrupt mask bit It becomes 1 by software reset 0 Interrupt to CPU by FERR of STATUS register is not masked 1 Interrupt to CPU by FERR of STATUS register is masked 27 TXUD0M This i...

Page 744: ...U by RXOVR of STATUS register is masked 18 EOPM This is interrupt mask bit by EOPI of STATUS register It becomes 1 by software reset 0 Interrupt to CPU by EOPI of STATUS register is not masked 1 Interrupt to CPU by EOPI of STATUS register is masked 17 RXFDM This is reception DMA request mask bit It becomes 1 by software reset 0 DMA transfer is requested when reception data written to reception FIF...

Page 745: ... value is threshold value or more The timer is cleared When the timer becomes time out EOPI bit of STATUS register is set to 1 The timer becomes 00 by software reset 00 0 the timer is not in operation 01 54000 AHB clock cycles 10 108000 AHB clock cycles 11 216000 AHB clock cycles 3 0 RFTH 3 0 Threshold value of reception FIFO is set Number of reception word written to reception FIFO is threshold v...

Page 746: ...free running mode FRUN 1 of CNTREG When FERR is 1 and FERRM of INTCNT register is 0 interrupt to CPU occurs Writing 1 from CPU clears the value to 0 This becomes 0 by software reset 28 TXUDR1 When transmission FIFO underflows at the top of frame the value is set to 1 Writing 1 from CPU clears the value to 0 This becomes 0 by software reset 27 TXUDR0 When transmission FIFO underflows during frame t...

Page 747: ...automatically to 0 The value is also become 0 when start bit of start register is 0 and TXENB bit of OPRREG register is 0 If software reset is performed at start bit 1 and TXENB bit 1 the value becomes 0 during software reset then changes to 1 after the process 16 RXFI When number of reception FIFO data is larger than the threshold set in RFTF of INTCNT register this bit is set to 1 This bit is 1 ...

Page 748: ...ot sent to DMAC I2S automatically clears TDMACT every time DMA packet transmission completes Writing 0 from CPU clears the value to 0 This becomes 0 by software reset 0 Transmission channel of DMAC is stop that TXDREQ is unable to be detected 1 Transmission channel of DMAC is activated that TXDREQ is able to be detected 15 1 Reserved Reserved bits The write access is ignored The read value of thes...

Page 749: ...rnal master During the master mode I2S_SCKx clock can be output by dividing external clock I2S_external clock x or internal clock it is selectable at register Frame synchronous signal can be generated by free running or burst mode generated only when there is transmission data This module equips transmission reception FIFO and its depth varies depending on mode transmission only mode is 36 word 32...

Page 750: ... synchronous signal input empty frame is output Stop At the time of stop transmission FIFO becomes empty with having no data transfer from internal memory to I2S transmission FIFO To maintain start bit to 1 TXENB 1 Keep outputting frame synchronous signal in the free running mode When transmission FIFO becomes empty empty frame is output however do not output frame synchronous signal in the burst ...

Page 751: ...ame after bit becomes Start 1 and TXENB 1 When writing to transmission FIFO occurs with having it full set TXOVR to 1 If it is not input with the frame rate defined frame synchronous signal in the free running mode set FERR bit of the register to 1 If the next frame synchronous signal is input before completing 1 frame transmission in the burst mode set FERR bit of the register to 1 Note 1 TXDIS a...

Page 752: ...rame synchronous signal is kept outputting in the free running mode frame is not received In the burst mode frame is not received and the signal is not output To make start bit 0 Write 0 to start bit then reception FIFO becomes empty Clock supply to the serial control part stops regardless of RXENB setting and I2S_SCKx supply to the external part is stop as well To maintain start bit to 1 Receptio...

Page 753: ... The same operation as reception only mode Status of Start 1 TXENB 1 and RXENB 1 Frame synchronous signal is output from the state that transmission FIFO is not empty and reception FIFO is not full After completion of 1 frame output or at idle state always confirm transmission reception FIFO status If transmission FIFO is not empty and reception FIFO is not full output frame synchronous signal to ...

Page 754: ... becomes empty in order to maintain this bit to TXENB 1 When the value is changed to 0 transmission FIFO becomes empty and transmission serial data bus becomes in high impedance Do not send the data in transmission FIFO at writing 0 to TXENB Stop writing to transmission FIFO Reception stop Write 0 to RXENB then reception FIFO becomes empty and frame reception operation stops To make start bit 0 Wr...

Page 755: ...n Master mode MSMD 1 Slave mode MSMD 0 Note 1 TXDIS and RXDIS are for setting to enable and disable transmission reception of CNTREG register 2 start TXENB and RXENB are operation control bits of OPRREG register 3 Empty frame bit is determined by MSKB of CNTREG register ...

Page 756: ...te 2 Number of channel of 1 sub frame is determined by S0CHN of MC0REG register Up to 32 channels are settable 3 Each channel bit length word length is determined by S0WDL of MC0REG register 4 Sub frame channel starts from 0th and each channel is settable to valid invalid with the corresponding bit of MC1REG register Transmission Reception of data is not performed to invalid channel 5 Dummy bit ca...

Page 757: ...nels are settable 3 Channel bit length word length of sub frame 0 is determined by S0WDL of MC0REG register For sub frame 1 they are determined by S1WDL of MC0REG register Since channel bit length of the sub frame is individual those channels word length do not need to be the same 4 Sub frame channel starts from 0th Each channel of sub frame 0 is settable to valid invalid with the corresponding bi...

Page 758: ...ccessing to TXFDAT on AHB bus Each FB0 FB1 FB2 FB3 FH0 FH1 and FW indicate AB0 AB1 AB2 AB3 AH0 AH1 and AW are written to transmission FIFO after they are right justified 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AB0 MSB LSB AB1 MSB LSB AB2 MSB LSB AB3 MSB LSB AH0 MSB LSB AH1 MSB LSB AW MSB LSB 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1...

Page 759: ...or less Byte 0 9 16 Half word 0 17 32 All words MSB First LSB First Serial data input pin s shifting direction B0B1B2B3B4B5B6B7 B7B6B5B4B3B2B1B0 B7B6B5B4B3B2B1B0 0 1 MLSB Bit extension and right justification BEXT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LSB BEXT 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSB BEXT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 LSB BEXT 0 0...

Page 760: ...rom reception pin To RXFDAT register R W From TXFDAT register To transmission pin TXDIS 0 and RXDIS 0 18 word X 32 bit 18 word X 32 bit Figure 27 6 Simultaneous transfer mode data flow With setting TXDIS 0 and RXDIS 0 of CNTREG register the mode becomes simultaneous transfer mode which operates in 66 word 32 bit transmission FIFO and reception FIFO ...

Page 761: ...m TXFDAT register From reception pin To transmission pin TXDIS 0 and RXDIS 1 18 word X 32 bit 18 word X 32 bit Figure 27 7 Transmission only mode data flow With setting TXDIS 0 and RXDIS 1 of CNTREG register the mode becomes transmission only mode which operates in 36 word 32 bit transmission FIFO and reception is not performed ...

Page 762: ...0 To RXFDAT register From TXFDAT register From reception pin To transmission pin 18 word 32 bit 18 word 32 bit Figure 27 8 Reception only mode data flow With setting TXDIS 1 and RXDIS 0 of CNTREG register the mode becomes reception only mode which operates in 36 word 32 bit reception FIFO and transmission is not performed ...

Page 763: ...as following features Programmable baud rate baud rate is selectable arbitrarily based on APB clock 16 byte transmission FIFO and 16 byte reception FIFO 28 3Block diagram Figure 28 1 shows block diagram of UART IRC_A DMAC Baud rate generator Register Transmitter FIFO shift Modem I F CPU I F Receiver FIFO shift INTR XTXRDY XRXRDY UART_SOUT0 UART_XRTS0 UART_SIN0 UART_XCTS0 APB bus UART ch5 UART ch0 ...

Page 764: ...T1 UART_SOUT2 UART_SOUT3 UART_SOUT4 UART_SOUT5 OUT 6 Output pin of serial data The number at the end of pin shows channel number of UART UART_XCTS0 IN 1 Input pin of modem control signal CLEAR TO SEND Only channel 0 of UART has this pin UART_XRTS0 OUT 1 Output pin of modem control signal REQUEST TO SEND Only channel 0 of UART has this pin 28 5Supply clock APB clock is supplied to UART Refer to 5 C...

Page 765: ...egister write only that is valid in DLAB 0 URT1DLL Divider latch register low order byte that is valid in DLAB 1 FFFE2004h URT1IER Interrupt enable that is valid in DLAB 0 URT1DLM Divider latch high order byte register that is valid in DLAB 1 FFFE2008h URT1IIR Interrupt ID register read only URT1FCR FIFO control write only FFFE200Ch URT1LCR Line control register FFFE2010h URT1MCR Modem control reg...

Page 766: ...that is valid in DLAB 0 URT4DLM Divider latch high order byte register that is valid in DLAB 1 FFF43008h URT4IIR Interrupt ID register read only URT4FCR FIFO control write only FFF4300Ch URT4LCR Line control register FFF43010h URT4MCR Modem control register FFF43014h URT4LSR Line status register read only FFF43018h URT4MSR Modem status register read only UART ch5 FFF44000h URT5RFR Reception FIFO r...

Page 767: ...tch register URTxDLL URTxDLM Address Base address Offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name R W Initial value Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name R W Initial valu e Meaning of item and sign Address Address base address offset address of the register Bit Bit number of the register Name Bit field name of the register R W Attribution of read write of each bit field R0...

Page 768: ...valid only at reading register and data is written to TFR register at DLAB 0 or DLL register at DLAB 1 according to the setting value of DLAB when writing 28 6 3 Transmission FIFO register URTxTFR Address ch0 FFFE_1000 00h ch1 FFFE_2000 00h ch2 FFF5_0000 00h ch3 FFF5_1000 00h ch4 FFF4_3000 00h ch5 FFF4_4000 00h Writing is enabled only at DLAB 0 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 N...

Page 769: ...X X X X X X X 0 0 0 0 0 0 0 0 Bit No Bit name Function 31 4 Unuse d Reserved bit input 0 at writing 3 EDSSI Enable Modem Status Interrupt When EDSSI is set to 1 and bit3 0 of the Modem status register is set interrupt occurs 2 ELSI Enable Receiver Status Interrupt When ELSI is set to 1 and bit4 1 of the Line status register is set interrupt occurs 1 ETBEI Enable Transmitter FIFO Register Empty Int...

Page 770: ...1 0 0 0 0 0 1 Bit No Bit name Function 31 8 Unused Reserved bit input 0 at writing 7 6 FIFO1 0 FIFO status Fixed to 11 5 4 00 3 0 ID2 0 NINT Interrupt setting 0001 No interrupt 0110 Reception line status 1 Top priority 0100 Reception data existed 2 1100 Time out 2 0010 Transmission FIFO is empty 3 0000 Modem status 4 Bit7 0 C1h after the reset Numerical value in is priority level When character ti...

Page 771: ...ed R W W W W W W W W W W W W W W W W W Initial valu e X X X X X X X X 0 0 0 0 0 0 0 0 Bit No Bit name Function 31 8 Unused Reserved bit input 0 at writing 7 6 RCVR1 0 Reception FIFO s trigger level 00 1 byte 01 4 byte 10 8 byte 11 14 byte 5 4 Unused Reserved bit 3 DMA MODE DMA transfer mode mode of XTXRDY and XRXRDY pins 0 Single transfer mode 1 Demand transfer mode Note Please use Demand mode to ...

Page 772: ...gister writes with address 0 IER register reads and writes with address 1 1 Enable DLL register reads and writes with address 0 DLM register reads and writes with address 1 TST register writes with address 7 6 SB Set Break break transmission 1 The SOUT signal forcibly becomes 0 5 SP Stick Parity fixed parity 0 Parity bit is determined by EPS and PEN 1 Parity bit is fixed as follows depending on th...

Page 773: ... R W R W R W R W R W R W R W R W R W R W R W Initial valu e X X X X X X X X 0 0 0 0 0 0 0 0 Bit No Bit name Function 31 8 Unused Reserved bit input 0 at writing 7 5 Unused Reserved bit input 0 at writing 4 LOOP Loop Back Mode self diagnostic mode When loop is set to 1 following is performed 1 SOUT becomes 1 2 SIN is separated from input Shift register of reception 3 Transmission shift register out...

Page 774: ...hift register and Transmission FIFO register become empty TEMT is set to 1 5 THRE Transmitter FIFO Register Empty transmission register empty When Transmission FIFO register is empty and ready to accept new data THRE is set to 1 This bit is cleared at sending data to Transmission shift register 4 BI Break Interrupt break reception This bit is set when SIN is held in 0 more than transmission time s...

Page 775: ...d input signal XRI is indicated Loop 1 It is equal to OUT1 of MCR 5 DSR Data Set Ready Loop 0 Inversed input signal XDSR is indicated Loop 1 It is equal to DTR of MCR 4 CTS Clear To Send Loop 0 Inversed input signal XCTS is indicated Loop 1 It is equal to RTS of MCR 3 DDCD Delta Data Carrier Detect This bit is set when DCD signal changes after the last reading by CPU The bit is reset by reading th...

Page 776: ... 7 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Initial valu e X X X X X X X X 0 0 0 0 0 0 0 0 DLM Address ch0 FFFE_1000 04h ch1 FFFE_2000 04h ch2 FFF5_0000 04h ch3 FFF5_1000 04h ch4 FFF4_3000 04h ch5 FFF4_4000 04h Accessing is enabled only at DLAB 1 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Reserved R W R W R W R W R W R W R W R W R W R W R W R W R W R W R ...

Page 777: ...100 1 136 19147 19200 100 3 90 28933 28800 99 5 68 38293 38400 100 3 45 57865 57600 99 5 23 113215 115200 101 8 Transmission baud rate on the other party and baud rate used by macro are able to receive data properly within the permissible error range Out of the range causes reception error Baud rate s permissible error range that macro permits is shown below 104 1 Macro baud rate 100 95 3 When bau...

Page 778: ...r 5 6 Reset End Figure 28 2 Example of initial setting 1 After the power on macro s each output pin is undefined Each output pin level becomes the one shown in the table of chapter 5 by inputting L to reset MR pin 2 Divider latch is able to be accessed by setting 1 to DLAB bit in the Line control register LCR register 3 Set baud rate clock refer to 28 6 11 Divider latch register URTxDLL URTxDLM 4 ...

Page 779: ...ble to be confirmed When they are empty TEMT becomes 1 c Transmission FIFO empty interrupt process When all data in transmission FIFO is moved to the Transmission shift register this interrupt occurs It is able to control approval prohibition in the Interrupt enable register URTxIER Note During transmission FIFO empty interrupt process check THRE bit of the LSR is 1 before writing data to transmis...

Page 780: ...D register IIR register at NINT 0 2 Type of interrupt is able to be observed by confirming ID0 ID1 and ID2 bit in the Interrupt ID register 3 After interrupt type is judged as reception line status interrupt with the process in item 2 reception error information is able to be acquired by reading the Line status register which also releases the interrupt INTR L 4 After interrupt type is judged as r...

Page 781: ...ugh it is full the last written data is deleted The data that is already stored in the transmission FIFO is properly transmitted THRE bit becomes 0 by writing to transmission FIFO When the writing data is transferred to the Transmission shift register and FIFO becomes empty the value becomes 1 If transmission data buffer interrupt is permitted in that time interrupt INTR pin becomes H and interrup...

Page 782: ...rst data of FIFO When reception data ready interrupt is permitted interrupt INTR pin becomes H and interrupt occurs by reaching the data in reception FIFO to the trigger level This interrupt is released when the data in the FIFO becomes less than the trigger level and interrupt INTR pin becomes L XRXRDY is data ready signal that shows possible reception to DMA controller at using the controller Si...

Page 783: ... D ATA 5 M ark state TEM T Transm i ssi on buffer W ri te Transm i ssi on buffer D ATA 3 CLK Figure 28 7 Example of operation of THRE flag and TEMT flag THRE flag 1 indicates that there is no data in the Transmission FIFO buffer register and transmission character is able to be written TEMT flag becomes 1 when there is no data in the register and Transmission shift register in the transmission con...

Page 784: ... becomes 1 The error flag is reset by reading Line status register When L level continues during transmission time start bit data bit parity bit and stop bit for 1 character break code is detected These errors are applied to each data in FIFO and they are able to be confirmed when CPU reads the first data of FIFO FE and BI flags are able to be confirmed in the Status register at reading Line statu...

Page 785: ...of 1 level bit in the 1 data bit When it is set to even parity with EPS in the Line control register the bit is set to 1 or 0 to have total data bit and 1 level parity bit even number Likewise when parity bit is set to odd parity total number of 1 level is set to be odd number On reception side the number of 1 level bit of 1 data including input parity bit is counted and polarity of the parity set...

Page 786: ...f bit 0 in the Line status register LSR is shown in Figure 28 11 1 character M ark state Start bi t Pari ty bi t D ata bi t Stop bi t UART_SI N x D R D 0 D 1 D 2 D 3 D 4 D 5 PT D 0 PT URTxRFR regi ster readi ng Figure 28 11 Operation example of DR flag When reception data is received and 1 byte or more of data is stored in reception FIFO DR flag of the Line status register becomes 1 The flag becom...

Page 787: ...is stored in reception FIFO and CPU still does not read the data after 4 characters of time When time out interrupt occurs INTR pin becomes H Moreover XRXRDY signal becomes L showing DMA controller that reception is ready and requests to read data Timer and time out interrupt are reset by CPU or DMA controller reading 1 byte from reception FIFO If time out does not occur it is reset after timer re...

Page 788: ...I2C_SCL1 exclusively use 3 3V so that the device can be used for 3 3V I 2 C communication I2C_SDA0 I2C_SDA1 are referred to as the SDA line and I2C_SCL0 I2C_SCL1 are referred to as the SCL line in this document 29 2Features The I 2 C modules have the following features Master transmission reception function Slave transmission reception function Arbitration function Clock synchronization function S...

Page 789: ...on Stop condition detector Arbitration lost detector Start condition Stop condition detector Shift Clock generator I2C_SDA0 I2C_SCL0 Noise filter I2C ADR APB bus I2C module 0 I2C module 1 I2C_SDA1 I2C_SCL1 MB86R01 Comparator I2C DAR I2C BSR I2C BCR I2C CCR I2C BC2R I2C ECSR I2C BCFR Figure 29 1 Block diagram of the I 2 C modules ...

Page 790: ...t register with following functions to show I 2 C bus status and others Repeated start condition detection Arbitration lost detection Acknowledge bit storage Direction of data transfer Addressing detection General call address detection First byte detection I2CxBCR 8 bit register that performs I 2 C bus control and interrupt control has following functions Interrupt request permission Start condit...

Page 791: ... pin name indicates the I2C channel number The output of this pin is open drain I2C_SDA0 I2C_SDA1 IN OUT 2 Data pin of the I2C bus interface The last number of the pin name indicates the I2C channel number The output of this pin is open drain 29 6Supply clock The APB clock is supplied to the I 2 C modules Refer to 5 Clock reset generator CRG for frequency setting and control specification of the c...

Page 792: ...C0CCR Clock control register FFF5600Ch I2C0ADR Address register FFF56010h I2C0DAR Data register FFF56014h I2C0ECSR Extension CS register FFF56018h I2C0BCFR Bus clock frequency register FFF5601Ch I2C0BC2R Bus control 2 register I 2 C ch1 FFF57000h I2C1BSR Bus status register FFF57004h I2C1BCR Bus control register FFF57008h I2C1CCR Clock control register FFF5700Ch I2C1ADR Address register FFF57010h ...

Page 793: ...13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name R W Initial valu e Meaning of item and sign Address Address base address offset address of the register Bit Bit number of the register Name Bit field name of the register R W Attribution of read write of each bit field R0 Read value is always 0 R1 Read value is always 1 W0 Write value is always 0 and write access of 1 is ignored W1 Write value is always 1 and w...

Page 794: ...e Bit 6 RSC Repeated Start Condition Repeated start condition detecting bit RSC State 0 Repeated start condition is not detected 1 Start condition is detected again during bus is in use This bit is cleared by writing 0 to the INT bit Start condition detection at bus stop and stop condition detection as well as addressing are not performed by the slave Bit 5 AL Arbitration Lost Arbitration lost det...

Page 795: ...tion bit AAS State 0 Addressing is not performed by slave 1 Addressing is performed by slave This is cleared on start condition detection or stop condition detection Bit 1 GCA General Call Address This is general call address 00h detecting bit GCA State 0 General call address is not received at slave 1 General call address is received at slave This bit is cleared on start condition detection or st...

Page 796: ... flag bit For writes BER State 0 Bus error interrupt request flag is cleared 1 N A For reads BER State 0 Bus error is not detected 1 Incorrect start and stop conditions are detected during data transfer When this bit is set the EN bit of the I2CxCCR register is cleared this module enters the halt state and the data transfer is discontinued Bit 6 BEIE Bus Error Interrupt Enable This is the bus erro...

Page 797: ...ly with this module as well as using arbitration lost for this module at the second byte or later Bit 3 ACK ACKnowledge This is the acknowledge permission bit at receiving data On reads writes ACK State 0 Acknowledge has not occurred 1 Acknowledge has occurred This bit is disabled on address data reception in slave mode Bit 2 GCAA General Call Address Acknowledge This is the acknowledge permission...

Page 798: ...he SCL line opens and the next byte is transferred In addition this is cleared to 0 by an occurrence of a start condition or a stop condition in master mode Competition of SCC MSS and INT bits Competition of the next byte transfer start condition and stop condition occurs by writing to the SCC MSS and INT bits simultaneously The priority order in this case is as follows 1 Occurrence of the next by...

Page 799: ... R R R R R R R R W R W R W R W R W R W R W Initial valu e 0 0 0 0 0 0 0 0 1 0 0 X X X X X Bit 7 Unused The value is always read as 1 Bit 6 HSM High Speed Mode This is the standard high speed setting bit At reading writing HSM State 0 Standard mode 1 High speed mode Bit 5 EN ENable This is the operation permission bit At reading writing EN State 0 Operation is prohibited 1 Operation is permitted Wh...

Page 800: ...φ φ Be sure to set fscl so that it doesn t exceed the following values during master operation Standard mode 100KHz High speed mode 400KHz The APB clock φ of this module should be used within the range shown below If it is less than the range transmission at the max transfer rate is not guaranteed If it exceeds the range the upper limit of the bus clock frequency can be extended by setting the I2C...

Page 801: ...ting prohibited 0 0 1 1 0 71 Setting prohibited 0 0 1 1 1 72 Setting prohibited 0 1 0 0 0 73 9 0 1 0 0 1 74 10 0 1 0 1 0 75 11 0 1 0 1 1 76 12 0 1 1 0 0 77 13 0 1 1 0 1 78 14 0 1 1 1 0 79 15 0 1 1 1 1 80 16 1 0 0 0 0 81 17 1 0 0 0 1 82 18 1 0 0 1 0 83 19 1 0 0 1 1 84 20 1 0 1 0 0 85 21 1 0 1 0 1 86 22 1 0 1 1 0 87 23 1 0 1 1 1 88 24 1 1 0 0 0 89 25 1 1 0 0 1 90 26 1 1 0 1 0 91 27 1 1 0 1 1 92 28 1...

Page 802: ...0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Reserved Reserved A 6 0 R W R R R R R R R R R R W R W R W R W R W R W R W Initial valu e 0 0 0 0 0 0 0 0 1 X X X X X X X Bit 7 Unused The value is always read as 1 Bit 6 0 A6 0 Address 6 0 This is the slave address storage bit The comparison with the I2CxDAR register is performed after address data reception at the slave If they are ...

Page 803: ... R R W R W R W R W R W R W R W R W Initial valu e 0 0 0 0 0 0 0 0 X X X X X X X X Bit 7 0 D7 0 Data 7 0 This is the serial data storage bit This data register is used for serial transfer transmitted from MSB When data is received TRX 0 the data output becomes 1 This register s writing side is double buffered so that writing data is loaded to the serial transfer register on the transmission of each...

Page 804: ... Bit 5 SDAS SDA status Indicates the signal level of the SDA line after passing the noise filter Only reading is valid SDAS State 0 The SDA line is 0 1 The SDA line is 1 Bit 4 SCLS SCL status Indicates the signal level of the SCL line after passing the noise filter Only reading is valid SCLS State 0 SCL line is 0 1 SCL line is 1 Bit 3 and 2 Unused The value is always 00 on reads Bit 1 SDAL SDA low...

Page 805: ... Reserved CS 10 5 R W R R R R R R R R R R R W R W R W R W R W R W Initial valu e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 5 0 CS10 5 Clock Period Select 10 5 This is set to expand the upper limit of the bus clock frequency by extending CS4 0 in the I2CxCCR register The initial value of CS10 5 is 000000 and setting other values enters the frequency upper limit expansion mode CS10 5 State 000000 No upper...

Page 806: ...odule within the range shown below If it is less than the range transfer at the max transfer rate is not guaranteed If it exceeds the range operation is not guaranteed Master operation 14MHz 41 5MHz Slave operation 14MHz 41 5MHz Register access operation 14MHz 41 5MHz Note 2 cycle is the min overhead for the detection of the output level change of the SCL line If the rising edge delay of the SCL p...

Page 807: ... 0 0 0 0 0 1 Bit 7 and 4 Unused The value is always 0000 on reads Bit 3 0 FS3 0 Bus Clock Frequency Select 3 0 Selects the frequency of the bus clock to be used Characteristics such as noise filters are set using this register A standard setting value is shown below however adjustment might be required depending on the I 2 C buffer characteristics and noise state on the I 2 C bus FS3 FS2 FS1 FS0 F...

Page 808: ...start condition can be incurred again by writing a 1 to the SCC bit even if the bus is in use BB 1 There are 2 ways to initiate a start condition 1 Writing 1 to the MSS bit in status MSS 0 BB 0 INT 0 AL 0 so that the bus is not used 2 Writing 1 to the SCC bit in interrupt status MSS 1 BB 1 INT 1 AL 0 on bus master If a 1 is written to the MSS bit during idle the AL bit is set to 1 Writing a 1 to t...

Page 809: ...to slave mode The following show the generation of a stop condition Writing a 0 to the MSS bit in interrupt status MSS 1 BB 1 INT 1 AL 0 on bus master Writing a 1 to the MSS bit in states other than the above is ignored Stop condition on the I2 C bus Changing the SDA line from 0 to 1 while the SCL line is 1 is called the stop condition I2C_SDAx I2C_SCLx Stop condition ...

Page 810: ...ge is sent to the master Then bit 0 of the reception data I2CxDAR register s bit 0 after reception is stored in the TRX bit Example of a slave address transmission Target slave address 0x76 Slave ADR register Send 0xEC Master DAR register Explanation b1110 1100 0xEC is derived from b0111 0110 0x76 left shifted by 1 bit with a 0 added as the LSB see also format description below Transfer format of ...

Page 811: ...29 24 MB86R02 Jade D Hardware Manual V1 64 ...

Page 812: ... the SCL line status and automatically adjusts the line s operation timing by adapting to the speed of the slowest device I2C_SCLx SCL output before arbitration Macro A Macro B Take timing from when SCL line becomes H to the next SCL output L Take timing from when SCL line becomes H to the next SCL output L SCL output after arbitration SCL output before arbitration SCL output after arbitration ...

Page 813: ... occurs although an unused bus is confirmed and MSS 1 is set then AL 1 is set and arbitration is lost If the AL bit is set to 1 the status becomes MSS 0 and TRX 0 and the state changes to slave reception mode If arbitration is lost the right to use the bus is lost the master discontinues to drive the SDA line However driving the SCL line is not discontinued until 1 byte of the transmission ends an...

Page 814: ... an acknowledge is not received from the master reception side during slave transmission when a negative acknowledge is received the state becomes TRX 0 and the mode changes to slave reception mode As a result the master is able to generate a stop condition when the slave opens the SCL line I2C_SDAx I2C_SCLx SDA output Macro A transmission Macro B reception Reception side returns ACK NACK to trans...

Page 815: ...r and this module stops a Detection of basic rule violation on I 2 C bus in data transmission including ACK bit b Detection of stop condition on master c Detection of basic rule violation on I 2 C bus on bus idle I2C_SDAx 1 Start 3 I2C_SCLx 2 D7 D5 D6 I2C_SDAx is changed in I2C_SCLx H during data transfer which leads to bus error ...

Page 816: ...tialization Start Slave address setting Clock frequency setting Macro enable setting Interrupt setting End I2CxADR offset 0Ch Write I2CxCCR offset 08h Write CS 4 0 Write EN 1 write I2CxBCR offset 04h Write BER 0 write BEIE 1 write INT 0 write INTE 1 write ...

Page 817: ...nowledge Interrupt Stop condition End Master I2CxDAR offset 10h Write MSS 1 write BB set and TRX set LRB reset Slave INT set and TRX set DAR write INT 0 write INT set LRB reset INT set and TRX reset ACK 1 write INT 0 write MSS 0 write INT reset BB reset and TRX reset AAS set BB set and TRX reset INT set I2CxDAR offset 10h Read INT 0 write BB reset and TRX reset AAS reset ...

Page 818: ...wledge Interrupt Stop condition End Master I2CxDAR offset 10h Write MSS 1 write BB set and TRX set LRB reset Slave INT set and TRX reset ACK 0 write INT 0 write INT set I2CxDAR Read LRB set and TRX set INT set and TRX set I2CxDAR offset 10h Write INT 0 write MSS 0 write INT reset BB reset and TRX reset AAS set BB set and TRX reset INT set INT 0 write BB reset and TRX reset AAS reset ...

Page 819: ...rror Start Error flag release Clock frequency setting Macro enable setting Interrupt setting End I2CxBCR offset 04h Write BER 0 write BEIE 1 write I2CxCCR offset 08h Write CS 4 0 Write EN 1 Write I2CxBCR offset 04h Write BER 0 write BEIE 1 write INT 0 write INTE 1 write ...

Page 820: ...ress This module does not support a 10 bit slave address Therefore do not specify a slave address from 78H to 7BH for the module If a wrong address is specified an acknowledge is returned on receiving 1byte however normal transfer will not proceed Competition of the SCC MSS and INT bits Simultaneous writing to the SCC MSS and INT bits causes competition between start and stop conditions on the nex...

Page 821: ...gle master environment This module is used in a multimaster environment however it does not send a general call address This module is used in a multimaster environment however other modules do not use a general call address transmission Although this module is used in a multimaster environment and other masters send general call address simultaneously with this module it does not lose arbitration...

Page 822: ...mentations of this module 30 2Features The SPI unit has the following features Full duplex serial synchronous transmission The following parameters of the transfer format are configurable a Bit rate b Data length 1 32 bit c Clock polarity d Phase Supports 2 types of slave select signals Only 1 slave is connectable Example of SPI connection Figure 30 1 shows an SPI connection example Figure 30 1 Ex...

Page 823: ...G State machine Control logic 32bit shift register Data register APB BUS 32bit 41 5MHz SIRQ SPI_SCK SPI_DO SPI_DI SPI_SS IRC Figure 30 2 Block diagram of SPI 30 4Supply clock The APB clock is supplied to the SPI unit Please refer to the chapter Clock Reset Generator CRG for details about setting the frequency and controlling the clock ...

Page 824: ...nternal logic is initialized except certain part Setup SETUP Stand by state of communication between master and slave SPI changes state in the following cases SPE bit of SPI slave control register SPISCR is set to 1 in the sleep state Communication completes properly in the busy state Received data should be read in the setup state Busy BUSY Communicating state with SPI slave Writing SPI data regi...

Page 825: ...l register SPI0SCR This sets SPI slave fixed setting 08H SPI 0 data register SPI0DR This writes and reads data to be transmitted received to SPI slave 0CH SPI 0 status register SPI0SR This maintains SPI state Address Register Abbreviation Description Base Offset FFF4_5000H 00H SPI 1 control register SPI1CR For general SPI settings 04H SPI 1 slave control register SPI1SCR This sets SPI slave fixed ...

Page 826: ... 11 10 9 8 7 6 5 4 3 2 1 0 Name R W Initial value Meaning of item and sign Address Address base address offset address of the register Bit Bit number of the register Name Bit field name of the register R W Attribution of read write of each bit field R0 Read value is always 0 R1 Read value is always 1 W0 Write value is always 0 and write access of 1 is ignored W1 Write value is always 1 and write a...

Page 827: ...ial value X X X X X 0 0 0 X X X X X X 0 0 Note This register should be accessed in 32 bit unit Bit field Description No Name 31 19 Unused bits The write access is ignored The read value of these bits is always 0 18 17 Unused bits The write access is ignored 16 SPL0 Polarity of SPI_SS pin slave selection pin is specified 0 Active high initial value 1 Active low 15 11 Unused bits The write access is...

Page 828: ...gure 30 4 Timing at CPHA 0 or 1 and CPOL 1 is shown in Figure 30 5 SPI_SCK CPHA 0 SPI_SCK CPHA 1 SPI_DI Shift in SPI_DI Shift out Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Figure 30 4 Timing of serial data and serial clock at CPOL 0 SPI_SCK CPHA 0 SPI_SCK CPHA 1 SPI_DI Shift in SPI_DI Shift out Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Figure 30 5 Timing of serial data and serial clock at CPOL 1 ...

Page 829: ...me 31 29 Unused bits The write access is ignored The read value of these bits is always 0 28 SPE SPI s clock supply is controlled 0 Clock supply to internal logic stops except certain part initial value 1 Clock is supplied to all the circuits Write 1 to operate SPI Its state changes from sleep to setup by setting SPE bit It changes to sleep by clear at the same time internal logic is reset except ...

Page 830: ...e mode after communicating this becomes active 4 SAUT Operation timing of slave selection is specified according to the combination of SMOD bit 0 Slave selection synchronizes with SSP bit s setting value regardless of SMOD see Figure 30 6 initial value 1 1SCK of wait is added from SPI data register SPIDR writing to serial data transmission and from the last data transmission to asserting negating ...

Page 831: ...IRQ SPI_SS SPI_DO SSP Assert SPIDR Write SSP Negate SPISR Read BUSY Figure 30 6 Timing chart of SPI_SS pin at SAUT 0 First Last SIRQ SPI_SS SMOD 0 DPI_DO SPIDR Write BUSY 1SCK 1SCK SIRQ SPI_SS SMOD 1 STL BUSY Figure 30 7 Timing chart of SPI_SS pin at SAUT 1 ...

Page 832: ... 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note This register should be accessed in 32 bit unit Do not operate this register in the busy state Bit field Description No Name 31 0 D31 0 Transmission Reception data to SPI slave is sto...

Page 833: ...he communication or stand by initial value 1 Communication is completed SIRQ pin outputs this bit It is cleared by reading SPISR register Figure 30 6 and Figure 30 7 show timing chart 6 3 Unused bits The write access is ignored The read value of these bits is always 0 2 SERR Operation error is indicated 0 Normal operation is in process initial value 1 Prohibited operation occurs Clear SPE bit of S...

Page 834: ...EEP STATE ERROR Write SPISCR SPE set clear Write SPICR STATE SETUP DATA communication No Yes Yes No STATE BUSY Read SPISR SIRQ clear Write SPIDR TxRx start STATE SETUP No Yes DATA Communication start Delete received data Read SPIDR Continue data communication without setting change DATA communication end Yes No Yes No Figure 30 8 SPI setup flow chart ...

Page 835: ...ng website for the CAN module specification URL http www semiconductors bosch de en ipmodules can canipmodules c_can c_can asp 31 1Outline MB86R02 incorporates a 2 port CAN interface which is in compliance with CAN protocol version 2 0 part A and B 31 2Block diagram Figure 31 1 shows a block diagram of the CAN module Figure 31 1 CAN Block diagram ...

Page 836: ...sters are allocated by word address units 32 bit for the local address of CAN thus the valid data in 32 bit width data of the APB Bus is 16 bit Table 31 1 CAN 0ch register map Register address CAN 0ch register address APB Bus data 31 0 FFF5_4000h 00h 0x0000 16 bit data FFF5_4004h 02h 0x0000 16 bit data FFF5_4008h 04h 0x0000 16 bit data Table 31 2 CAN 1ch register map Register address CAN 1ch regis...

Page 837: ...g document OS62400 MediaLB Device Interface Macro Advanced Product Data Sheet DS62400AP5 32 1 Outline MB86R02 incorporates one MediaLB interface port which supports up to 16 channels 32 2 Block diagram Figure 32 1 shows a block diagram of the MediaLB module AHB slave AHB bus MediaLB I O Port MB86R02 AHB master MediaLB macro Media local bus MediaLB controller MOST network IRC MLB_CINT MLB_SINT MLB_...

Page 838: ... refer to 5 Clock reset generator CRG for information about setting the frequency and the control specifications of the AHB clock 32 4 Registers The registers of this GDC are mapped in byte addresses 8 bit however local addresses of the MediaLB module are accessed using word addresses 32 bit Register address MediaLB local address FFF6_0000h 00h FFF6_0004h 01h FFF6_0008h 02h ...

Page 839: ...Hardware Manual V1 64 33 SD Memory Controller SDMC Only SD card licensees can be given this information Please contact us at https www s fujitsu com emea services microelectronics gdc gdc enquiryform index html for details ...

Page 840: ...imum ratings voltage current temperature etc may cause damage to semiconductor devices Never exceed the ratings above Do not connect an IC output or I O pin directly or connect them to VDD or VSS directly as the thermal destruction of elements might occur except for those pins designed for output timing Provide ESD protection such as grounding when handling the product otherwise an externally gene...

Page 841: ...ature TJ 40 125 C Table 34 3 3 3V Standard CMOS I O Recommended Operating Conditions Parameter Symbol Min Typ Max Unit Power supply voltage VDE DDRVDE 1 7 1 8 1 9 V VDDI 1 10 1 20 1 30 V Junction temperature TJ 40 125 C The recommended operating conditions for the standard SSTL_18 excerpted from JESD8 15a Table 34 4 SSTL_18 Recommended Operating Conditions Note The recommended operating conditions...

Page 842: ... if the following condition is met Figure 34 2 Do not apply VDDE and DDRVDE external continuously for more than 1 second when VDDI internal is off VDDE APIXVD33 1 sec or less VDDI APIXVD12 1 sec or less DDRVDE Figure 34 2 Recommended Power On Off Sequence 2 Perform power on off for VREF according to the DDR2 SDRAM regulation Perform power on off so that power for PLLVDD PLL does not exceed VDDI Tu...

Page 843: ...image not the actual one Internal clock generated by ECLK or XTAL Input L when power on Input clock immediately after power on PLL Lockup Time VDDI internal Input L when power on 8 µs or more XSRST output L when power on Input when XRST is H after L Figure 34 3 Power On Sequence Input XTRST and XRST pins to Low when power on Keep XTRST and XRST pins High after setting to Low level for 8µs or more ...

Page 844: ...indicate the following external pins Driving capability 1 MEM_ED_0 MEM_ED_1 MEM_ED_2 MEM_ED_3 MEM_ED_4 MEM_ED_5 MEM_ED_6 MEM_ED_7 MEM_ED_8 MEM_ED_9 MEM_ED_10 MEM_ED_11 MEM_ED_12 MEM_ED_13 MEM_ED_14 MEM_ED_15 MEM_EA_1 MEM_EA_2 MEM_EA_3 MEM_EA_4 MEM_EA_5 MEM_EA_6 MEM_EA_7 MEM_EA_8 MEM_EA_9 MEM_EA_10 MEM_EA_11 MEM_EA_12 MEM_EA_13 MEM_EA_14 MEM_EA_15 MEM_EA_16 MEM_EA_17 MEM_EA_18 MEM_EA_19 MEM_EA_20 M...

Page 845: ...SIN0 UART_SOUT0 UART_SIN1 UART_XCTS0 UART_SOUT1 SPI_DI0 UART_XRTS0 UART_SIN2 SPI_DO0 SPI_DI1 UART_SOUT2 SPI_SS0 SPI_DO1 SPI_SS1 SPI_SCK0 SPI_SCK1 RTCK XSRST TRACEDATA_0 TRACECTL TRACEDATA_1 TRACEDATA_2 TRACEDATA_3 In LV TTL Mode DISP1P DISP1N DISP11P DISP11N DCLKP DCLKN Driving capability 3 DCLKO1 ...

Page 846: ... Standard CMOS I O V I Characteristic Driving Capability 1 Conditions MIN Process Slow TJ 125 C VDDE 3 0 V TYP Process Typical TJ 25 C VDDE 3 3 V MAX Process Fast TJ 40 C VDDE 3 6 V Figure 34 4 3 3V Standard CMOS I O V I Characteristic Driving Capability 1 ...

Page 847: ... Standard CMOS I O V I Characteristic Driving Capability 2 Conditions MIN Process Slow TJ 125 C VDDE 3 0 V TYP Process Typical TJ 25 C VDDE 3 3 V MAX Process Fast TJ 40 C VDDE 3 6 V Figure 34 5 3 3V Standard CMOS I O V I Characteristic Driving Capability 2 ...

Page 848: ...Standard CMOS I O V I Characteristics Driving Capability 3 Conditions MIN Process Slow TJ 125 C VDDE 3 0 V TYP Process Typical TJ 25 C VDDE 3 3 V MAX Process Fast TJ 40 C VDDE 3 6 V Figure 34 6 3 3 V Standard CMOS I O V I Characteristic Driving Capability 3 ...

Page 849: ... DC Logic Levels Differential Ended Symbol Parameter Min Max Unit VIN DC DC input signal voltage 300 VDDQ 300 mV VID DC DC differential input voltage 250 VDDQ 600 mV Table 34 10 SSTL18 Input AC Logic Levels Differential Ended Symbol Parameter Min Max Unit VID AC AC differential input voltage 500 VDDQ 600 mV VIX AC AC differential cross point voltage 0 5 VDDQ 175 0 5 VDDQ 175 mV Table 34 11 SSTL18 ...

Page 850: ...parameters Symbol Parameter Min Max Unit VOX AC differential cross point voltage 0 5 VDDQ 125 0 5 VDDQ 125 mV Note External pin for DDR2SDRAM IO buffer is as follows MDQSP 3 0 MDQSN 3 0 MDM 3 0 MDQ 31 0 MCKP MCKN MA 13 0 MBA 1 0 MCAS MCKE MCS MRAS MWE ODTCONT OCD ODT VREF0 VREF1 ...

Page 851: ...ause the charge current for decoupling capacitors is supplied through the reference resistance it takes about 2ms to get the correct result it is the case decoupling capacitor is 0 1µF Table 34 15 ADC Characteristics VDD 1 2V AVD 3 0V FS 100KS s FC 1 4MHz FVIN 1 kHz TA 25 C 1 Parameter Symbol Value Unit Min Typ Max Supply current included reference current AD_AVD0 0 8 1 2 mA 1 50 µA Reference volt...

Page 852: ...34 13 MB86R02 Jade D Hardware Manual V1 64 3 1LSB VFST VZT 1022 INLn 1LSBxn VZT Vn 1LSB DNLn Vn 1 Vn 1LSB 1 ...

Page 853: ...ll Bus capacitance 10 pF 400 pF VIH min to VIL max tof 250 20 0 1Cb 3 250 ns Data line leakage Input voltage 0 1 0 9 VDDE max Ii 10 10 10 10 µA I O pin capacitance Ci 10 10 pF 1 The I 2 C Bus Fast Mode I O buffer is downward compatible with standard mode 2 90nm Technology Complies with the maximum ratings 4 V 3 Cb Capacitance for 1 bus line Unit pF 4 The I 2 C Bus Fast Mode I O buffer itself has n...

Page 854: ...34 15 MB86R02 Jade D Hardware Manual V1 64 34 4 4 1 I2C IO V 1 Characteristic Figure Figure 34 7 I 2 C V I Characteristic Figure ...

Page 855: ...lect delay time 11 ns MEM_EA 24 1 tao Address delay time 11 ns MEM_ED 31 0 tdo Data output delay time 11 ns tdoz Data output HiZ time 12 ns tdsr SRAM NOR Flash data setup time 18 ns tdhr SRAM NOR Flash data hold time 0 ns tdsp NOR Flash page Read data setup time 18 ns tdhp NOR Flash page Read data hold time 0 ns MEM_XRD trdo XRD delay time 11 ns MEM_XWR 3 0 twro XWR delay time 11 ns Standard clock...

Page 856: ...EM_XCS4 MEM_EA 24 1 MEM_XRD MEM_ED 31 0 tcso tao tdsr tdhr MEM_RDY trdo trdo tcso tao Figure 34 8 SRAM NOR Flash Read Internal CLK MEM_XCS0 MEM_XCS2 MEM_XCS4 MEM_EA 24 1 MEM_XWR 1 0 MEM_ED 31 0 tcso tao MEM_RDY twro twro tdo tdo X tcso tao tdo Figure 34 9 SRAM NOR Flash Write ...

Page 857: ...cso tao tdsr tdhr MEM_RDY trdo Min 2Cycle Internal CLK trdo Min 0 ns trdo tcso tao Figure 34 10 Low speed device Read Internal CLK MEM_XCS0 MEM_XCS2 MEM_XCS4 MEM_EA 24 1 MEM_XWR 1 0 MEM_ED 31 0 tcso tao MEM_RDY twro twro tdo tdo X tcso tao tdo Min 2Cycle Internal CLK twro Min 0 ns Figure 34 11 Low speed device Write ...

Page 858: ...34 19 MB86R02 Jade D Hardware Manual V1 64 Internal CLK MEM_XCS0 MEM_XCS2 MEM_XCS4 MEM_EA 24 1 MEM_XRD MEM_ED 31 0 tcso tao tdsp tdhp MEM_RDY tcso tao trdo tao tdsp tdhp Figure 34 12 NOR Flash Page Read ...

Page 859: ...k 6ns 333Mbps is indicated Table 34 19 Write Spec 3 DQ DQS Item Symbol Spec formula Criteria value 1 Unit Min Typ Max DQ DM setup valid data from DQS tVD_setup_DQ tCK 4 884 616 ps DQ DM hold valid data from DQS tVD_hold_DQ tCK 4 776 724 ps 1 Spec for tck 6ns 333Mbps is indicated Table 34 20 Read Spec 1 DQ DQS Item Symbol Spec formula Criteria value 1 Unit Min Typ Max tSETUP DQ from DQS tSETUP_DQ 0...

Page 860: ...Hardware Manual V1 64 34 5 2 1 DDR2SDRAM Interface Timing Diagram Figure 34 13 Timing Regulation Point DDR2 SDRAM DDR2 400 CK CMD AD DQ DQS MB86R01 Timing regulation point DDR2C External load condition PCB design guideline ...

Page 861: ...CK CMD ADD and CK DQS Figure 34 15 Write Spec 3 DQ DQS CK_out CK_out tSkew_DQS_CK CMD ADD_out tVD_setup_CMD tVD_hold_CMD DQS_out tSkew_DQS_CK Valid Data tCK 6ns 166MHz DQS_out DQ_out DM_out tVD_hold_DQ Valid Data2 Valid Data1 Valid Data0 Valid Data3 tVD_setup_DQ tCK 6ns 166MHz ...

Page 862: ...4 Figure 34 16 Read Spec 1 DQ DQS Figure 34 17 Read Spec 2 DQS R T T RoundTrip Time C K_ Ou tCK 6ns 166MHz DQS_in delay Min DQS_in delay Max tRTT_DQS Min tRTT_DQS Max CL 3 or 3 DQS_in DQ_in tSETUP_DQ tCK 6ns 166MHz tHOLD_DQ tHOLD_DQ tSETUP_DQ ...

Page 863: ...ription Value Unit Min Typ Max GPIO_PD 23 0 tdo Data output delay time 13 ns tdw Input data width A Ns Internal clock is the standard of output delay A indicates APB bus clock cycle and it is different from the output delay standard clock Internal CLK GPIO_PD 23 0 Input tdo tdw Output Figure 34 18 GPIO Timings ...

Page 864: ...Table 34 23 AC Timing of Ide Data Input Signal Signal Symbol Description Value Unit Min Typ Max PWM_O0 T0 Output delay of PWM_O0 based on APB BusClock 2 0 14 0 ns PWM_O1 T1 Output delay of PWM_O1 based on APB BusClock 2 0 14 0 ns PWM_O0 APB BusClock T0 PWM_O1 T1 Figure 34 19 PWM Output Timing ...

Page 865: ... 3 Load Capacitance 20pF 4 Load Capacitance 30pF 34 5 5 2 Input Signal 1 Apply the signal only in PLL synchronization mode CKS 0 Reference clock Clock output from internal PLL Table 34 25 AC Timing of Video Interface Input Signal 1 Signal Symbol Description Value Unit Min Typ Max HSYNC0 i Twhsync0 HSYNC input pulse width 3 0 Clock HSYNC1 i Twvsync1 VSYNC input pulse width 3 0 Clock VSYNC0 i Twvsyn...

Page 866: ...34 27 MB86R02 Jade D Hardware Manual V1 64 VSYNC0 i Twvsync0 VSYNC input pulse width 1 HSYNC VSYNC1 i Twvsync1 VSYNC input pulse width 1 HSYNC ...

Page 867: ...nc0 VSYNC output delay time with TCON bypass active 1 0 6 0 ns VSYNC1 o Tdvsync1 VSYNC output delay time 0 6 3 6 ns DE0 CSYNC0 1 Tdcsync0 CSYNC output delay time with TCON bypass active 1 0 6 0 ns DE1 CSYNC1 Tdcsync1 CSYNC output delay time 0 6 3 6 ns GV0 1 Tdgv0 GV output delay time with TCON bypass active 1 0 6 0 ns GV1 Tdgv1 GV output delay time 0 6 3 6 Ns Load Capacitance 20pF except 1 Note If...

Page 868: ... DCLKOn inverted DCLKOn HSYNCn o 1 Fdclkon VSYNCn o DOUTRn 5 0 DOUTGn 5 0 DOUTBn 5 0 Tddrgbn CSYNCn GVn Tdhsyncn Tdvsyncn Tdcsyncn Tdgvn Figure 34 21 Display Output Signal Timing There is no definition of AC characteristics about analog signal ...

Page 869: ...1 RSHD hold time ns 2 9 RSSU setup time ns 2 4 C_L 30pF Delay i 12 1 Delay i 0 11 0 RSHD hold time ns 3 2 TSG_ 12 4 HSYNC0 VSYNC0 DE0 GV0 TSIGSU setup time ns 7 4 C_L 30pF Delay i 12 0 Delay i 0 11 1 SSWITCH i 0 TSIGHD hold time ns 7 4 TSIGSU setup time ns 11 9 C_L 30pF Delay i 12 1 Delay i 0 11 0 SSWITCH i 0 TSIGHD hold time ns 2 9 TSIGSU setup time ns 2 9 C_L 30pF Delay i 12 1 Delay i 0 11 0 SSW...

Page 870: ...K pin DISP j Register DIR_Pin_ctrl j Delay 0 TTLCKH TTLCKL 50 TTLDAT pins DISP i Registers DIR_Pin_ctrl i Delay 0 DISPHD DISPSU Pins TSIG i Register Dir_SSwitch SSwitch 0 TSIGHD TSIGSU Figure 34 2434 25 TTL operation output timing 1 TTLCKH TTLCKL 50 TTLDAT pins DISP i Registers DIR_Pin_ctrl i Delay 0 DISPHD DISPSU Pins TSIG i Register Dir_SSwitch SSwitch 0 TSIGHD TSIGSU TTLCK pin DISP j Register D...

Page 871: ...ency frsds Maximum output frequency in RSDS mode 67 MHz 34 5 8 GDC Video Capture Signal Timing 34 5 8 1 Clock Table 34 28 AC Timing of Video Capture Interface Clock Signal Signal Symbol Description Value Unit Min Typ Max CCLK0 CCLK1 fCCLK Capture clock frequency 80 MHz tHCCLK Capture clock H width 3 ns tLCCLK Capture clock L width 3 ns Note It depends on the resolution of the video source 34 5 8 2...

Page 872: ...t setup time 5 ns tHHSI Input hold Time 0 ns VINVSYNC0 VINVSYNC1 tSVSI Input setup time 5 ns tHVSI Input hold Time 0 ns VINFID0 VINFID1 tSFI Input setup time 5 ns tHFI Input hold Time 0 ns Figure 34 28 Video Capture Clock Input Signal Timing 1 fCCLK tLCCLK tHCCLK CCLK0 CCLK1 ...

Page 873: ...R02 Jade D Hardware Manual V1 64 tSVI tSRI tSGI tSBI tSHSI tSVSI tSFI VIN0 1 tHVI tHRI tHGI tHBI tHHSI tHVSI tHFI RI GI BI VINHSYNC0 1 VINVSYNC0 1 CCLK0 1 VINFID0 1 Figure 34 29 Video Capture Input Signal Timing ...

Page 874: ...r I2S_SCKx Low master mode 4 TODO ns Hold time I2S_SDIx valid after I2S_SCKx Low slave mode 0 ns Table 34 31 Switching Characteristics Signal Symbol Description Value Unit Min Typ Max I2S_SCKx tmcyc Operating frequency I2S_SCKx master mode 0 5B MHz tmhw Pulse duration I2S_SCKx high master mode 0 45T 0 55T ns tmlw Pulse duration I2S_SCKx low master mode 0 45T 0 55T ns I2S_WSx tdfs Delay time I2S_SC...

Page 875: ... tdfb1 tsdi thd i tsdi thd i tddo tsfi thfi tsfi thfi tsfi tsfi tscyc tshw tslw Figure 34 31 Slave Mode Timing FSPH is bit 2 of I2Sx_CNTREG register FSLN is bit 1 of I2Sx_CNTREG register I2S_SCKx I2S_WSx FSPH 0 FSLN 0 I2S_WSx FSPH 1 FSLN 0 I2S_WSx FSPH 0 FSLN 1 I2S_WSx FSPH 1 FSLN 1 I2S_SDOx I2S_SDIx tddo tdfs tdfs tdfs tdfs tdfs tdfb1 tdfs tdfs tsdi thd i tsdi thd i tdfs tmcyc tmhw tmlw ...

Page 876: ... UART_SIN4 UART_SIN5 tdw Input data width 16A ns UART_XRTS0 trtso XRTS output delay time 11 ns UART_XCTS0 tctsw Input XCTS data width A ns Internal clock is the standard of output delay A indicates APB bus clock cycle and it is different from the output delay standard clock Internal CLK UART_SOUT0 UART_SOUT1 UART_SOUT2 UART_SOUT3 UART_SOUT4 UART_SOUT5 UART_SIN0 UART_SIN1 UART_SIN2 UART_SIN3 UART_S...

Page 877: ...ode Int 1 5 m 2 2 PCLK 3 TWHSCLO SCLO H width Normal mode m 2 2 PCLK 3 High speed mode Int 0 5 m 2 2 PCLK 3 TWLSCLO SCLO L width Normal mode m 2 PCLK 3 High speed mode m 2 PCLK 3 TS2SCLI SCLI setup time Normal mode 4 0 2 µs High speed mode 0 6 2 µs TH2SCLI SCLI hold time Normal mode 4 7 2 µs High speed mode 1 3 2 µs 1 I 2 C bus specification value 2 See I 2 C bus interface s clock control register...

Page 878: ...etup time SPI_DI valid before SPI_SCK 10 ns thdi Hold time SPI_DI valid after SPI_SCK 0 ns SPI_DO tdo Delay time SPI_SCK 0 9 ns SPI_SS tsso Delay time SPI_SCK 0 9 ns A indicates APB bus clock cycle Load capacitance 30pF Analysis relative to falling SCK TODO SPI_SCK SPI_DI tdo tsdi SPI_DO tsso SPI_SS thdi SPI_SCK tcyc Figure 34 34 SPI Timing Polarity of SPI_SCK is determined by the register setting...

Page 879: ... CAN AC Timing Signal Symbol Description Value Unit Min Typ Max CAN_TX0 CAN_TX1 tdo Data output delay time 17 ns CAN_RX0 CAN_RX1 tdw Input data width 1000 ns Internal clock is the standard of output delay Internal CLK CAN_TX0 CAN_TX1 CAN_RX0 CAN_RX1 tdo tdw Figure 34 35 CAN Timing ...

Page 880: ...K low time 30 14 37 17 ns 256xFs 512xFs tmckh MLBCLK high time 30 14 38 17 ns 256xFs 512xFs tmpwv MLBCLK pulse width variation 2 ns pp 2 1 The controller can shut off MLBCLK to place MediaLB in a low power state 2 Pulse width variation is measured at 1 25V by triggering on one edge of MLBCLK and measuring the spread on the other edge measured in ns peak to peak pp 9 1 1 1 1 Input Signal Table 34 3...

Page 881: ...1 ns VIL to VIH tmckf MLBCLK falling time 1 ns VIH to VIL tmckc MLBCLK cycle time 20 3 ns tmckl MLBCLK low time 6 8 7 8 ns tmckh MLBCLK high time 9 7 10 4 ns tmpwv MLBCLK pulse width variation 0 5 ns pp 2 1 The controller can shut off MLBCLK to place MediaLB in a low power state 2 Pulse width variation is measured at 1 25V by triggering on one edge of MLBCLK and measuring the spread on the other e...

Page 882: ... ensure that the high impedance bus does not leave the logic state of the final driven bit for this time period Therefore coupling must be minimized while meeting the maximum capacitive load listed Figure 34 36 MediaLB Timing Figure 34 37 MediaLB Pulse Width Variation Timing ...

Page 883: ...put Signal Table 34 43 AC Timing of Data Signal Signal Name Symbol Description Value Unit Min Typ Max SD_DAT 3 0 SD_CMD tD_DAT Output data delay standard of SD_CLK falling edge 0 3 6 0 ns SD_DAT 3 0 SD_CMD SD_XMCD SD_WP tS_DAT Input data setup standard of SD_CLK rising edge 11 0 ns tH_DAT Input data hold standard of SD_CLK rising edge 0 0 ns Load Capacitance 30pF SD_CLK SD_DAT 3 0 SD_CMD tD_DAT tD...

Page 884: ...34 45 MB86R02 Jade D Hardware Manual V1 64 ...

Page 885: ... to falling edge of TRACECLK 2 ns Tctlhf TRACECTL hold time to falling edge of TRACECLK 1 ns TRACEDATA 3 0 Tdatasr TRACEDATA setup time to rising edge of TRACECLK 2 ns Tdatahr TRACEDATA hold time to rising edge of TRACECLK 1 ns Tdatasf TRACEDATA setup time to falling edge of TRACECLK 2 ns Tdatahf TRACEDATA hold time to falling edge of TRACECLK 1 ns TRACECLK TRACECTL Tctlsf NOTE MB86R01 supports on...

Page 886: ...INT_A 3 0 tdw Input data width A ns The case that external interrupt input request is edge rising edge and falling edge input data width tdw is regulated as follows When level H or L is selected as the request it should be held until interrupt process is completed A indicates APB bus clock cycle APB BUS CLK INT_A 3 0 tdw Figure 34 41 EXIRC Timing ...

Page 887: ...is adjustable The drive current is controlled by a digital 4 Bit Value 16 Steps The Driver and output currents increase monotonically with 4 bit control value upDataSwing 3 0 Parameter Symbol Rating Unit Min Typ Max Output Current upstream for Upstream swing upDataSwing 3 0 0x0 IData_Swing 3 4 4 0 4 6 mA upDataSwing 3 0 0x1 3 825 4 5 5 175 upDataSwing 3 0 0x2 4 335 5 1 5 865 upDataSwing 3 0 0x3 4 ...

Page 888: ...e Nominal de emphasis values are 0 17 33 50 34 5 18 4 Receiver Input Sensitivity Parameter Symbol Rating Unit Min Max Receiver differential input swing Vdiff_pk pk 120 1000 mV 34 5 18 5 Receiver Common Mode Parameter Symbol Rating Unit Min Max Common mode voltage Vcm APIXVSS 0 5 APIXVD12 0 5 V 34 5 18 6 Transmitter Serial Data Signal Characteristics The transmitter covered the total jitter require...

Page 889: ...XVDD 3 3V 3 0 3 3 3 6 V Power supply current I APIXVD33 29 46 mA 34 5 19 2 Crystal and Clock buffer Frequencies Parameter Symbol Rating Unit Min Typ Max Crystal resonant frequency Fosc 10 25 62 5 MHz Clock Buffer Input frequency Fclk 1 25 62 5 MHz 34 5 19 3 Internal Feedback Resistor Parameter Symbol Rating Unit Min Typ Max Internal Feedback Resistor Rfb 80 100 120 kΩ ...

Page 890: ...tial state for ES2 35 2Multiplex 2 The function and mode decoding of specific multiplex pins changed from ES1 to ES2 These tables show the states for the ES1 ES2 devices Note The first column of each of the following tables is the default state If a non specified MUX function is selected then the default MUX function is applied e g Pin Multiplex mode 0 11 first MUX function applies Pin multiplex m...

Page 891: ...erface 1 dot clock input PD SYSTEM PLLTDTRST E4 D I Test pin Pull up the pin to VDDE via high resistance PU DISP0 TSG_4 W1 D O TCON Timing Signal 4 L PD CAP0 VIN0_4 AB1 D I Video Capture Data Input 0 bit 4 HiZ PD CAP0 VIN0_5 AB2 D I Video Capture Data Input 0 bit 5 HiZ PD CAP0 VIN0_0 AC1 D I Video Capture Data Input 0 bit 0 HiZ PD CAP0 VIN0_6 AB3 D I Video Capture Data Input 0 bit 6 HiZ PD CAP0 VI...

Page 892: ...ts PD 35 4SSCG Spread Spectrum Modulation The functional scope of the SSCG Spread Spectrum Modulation and Clock Generation unit is slightly different for ES1 and ES2 versions of the MB86R02 Jade D Modulation of internal chip units and the memory clock domain Modulation of the display clock domain ES1 NO YES ES2 YES YES 35 5Polarity of JTAGSEL Please note that the polarity of JTAGSEL in MB86R02 Jad...

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