Fujitsu MB86R02, Hardware Manual

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18-29
MB86R02 ‘Jade-D’ Hardware Manual V1.64
18.6.7 DCLKO shift
1) Delay
If the internal PLL is used to generate the DCLK, then it is possible to delay the DCLKO signal. The
DCKD field in the DCM3 register defines a delay value in units of internal PLL clock cycles.
DCKD (value in hex.) Delay
0x00 No delay (res)
0x02 +1 PLL clock
0x04 +2 PLL clocks
0x06 +3 PLL clocks
0x08 +4 PLL clocks
0x0A +5 PLL clocks
0x0C +6 PLL clocks
0x0E +7 PLL clocks
0x10 +8 PLL clocks
0x12 +9 PLL clocks
0x14 +10 PLL clocks
0x16 +11 PLL clocks
0x18 +12 PLL clocks
0x1A +13 PLL clocks
0x1C +14 PLL clocks
0x1E +15 PLL clocks
2) Inversion
DCLKO inversion is also available with or without the delay functionality. This function is effective
without regard to the DCLK clock source.
The DCKinv bit of DCM3 enables this function.
18.6.8 Synchronous register updates and display
To update position related parameters without disturbing the display, it is necessary to update in synch
with the VSYNC interrupt and to complete this in time.
This synchronous register update mode eases this limitation. In this mode, written parameters are hold
in intermediate registers and update at once synchronously with VSYNC.
RUM-bit of DCM2 register enables this mode.
RUF-bit of DCM2 register controls start of update and shows whether update is done or not.