Fujitsu MB86R02, Hardware Manual

Page: 278 / 892

15-15
MB86R02 ‘Jade-D’ Hardware Manual V1.64
15.6.6 DMAC destination address register (DMACDAx)
Address
ch0
：
F1C (h) ch1
：
F2C (h) ch2
：
F3C (h) ch3
：
F4C
(h)
ch4
：
F5C (h) ch5
：
F6C (h) ch6
：
F7C (h) ch7
：
F8C
(h)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DMACDA[31:16]
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DMACDA[15:0]
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit field
Description
No. Name
31-0 DMACDA[31:0]
(DMAC
Destination
Address)
These bits are used to specify destination address to start DMA transfer, and they are
able to be read during DMA transfer.
When fixed address function (DMACB/FD) is disabled, these bits are incremented
according to the transfer width (DMACB/TB) after completing destination address
properly.
After DMA transfer, DMAC sets the next destination address to these bits.
[Note]
It is prohibited to set DMAC register address to DMACDA.
DMACDA Function
x(h) Destination address to start DMA transfer
(Initial value: 32'h00000000)